A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. - Karyofyllis Patsidis; Dimitris Konstantinou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (Microprocess. Microsystems, 2018)

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. - Ron Gabor; Yiannakis Sazeides; Arkady Bramnik; Alexandros Andreou; Chrysostomos Nicopoulos; Karyofyllis Patsidis; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DATE, 2019)

RISC-V2: A Scalable RISC-V Vector Processor. - Karyofyllis Patsidis; Chrysostomos Nicopoulos; Georgios Ch. Sirakoulis; Giorgos Dimitrakopoulos (ISCAS, 2020)

IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. - Yiannakis Sazeides; Alex Gerber; Ron Gabor; Arkady Bramnik; George Papadimitriou 001; Dimitris Gizopoulos; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos; Karyofyllis Patsidis (MICRO, 2022)