Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. - Patrik Kimfors; Niklas Broman; Andreas Haraldsson; Kasyab P. Subramaniyan; Magnus Själander; Henrik Eriksson; Per Larsson-Edefors (ICECS, 2009)

Layout exploration of geometrically accurate arithmetic circuits. - Kasyab P. Subramaniyan; Emil Axelsson; Per Larsson-Edefors; Mary Sheeran (ICECS, 2009)

Design space exploration for an embedded processor with flexible datapath interconnect. - Tung Thanh Hoang; Ulf Jalmbrant; Erik der Hagopian; Kasyab P. Subramaniyan; Magnus Själander; Per Larsson-Edefors (ASAP, 2010)

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. - Alen Bardizbanyan; Kasyab P. Subramaniyan; Per Larsson-Edefors (ISVLSI, 2010)

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. - Babak Hidaji; Salar Alipour; Kasyab P. Subramaniyan; Per Larsson-Edefors (ISVLSI, 2011)

Manufacturable nanometer designs using standard cells with regular layout. - Kasyab P. Subramaniyan; Per Larsson-Edefors (ISQED, 2013)