VHDL structural model visualization. - Dominik Macko; Katarína Jelemenská (EUROCON, 2011)

VHDLVisualizer: HDL model visualization with simulation-based verification. - Dominik Macko; Katarína Jelemenská (DDECS, 2012)

Extensible framework for graphical representation of HDL models and Simulation Results. - Katarína Jelemenská; Martin Hyben; Tomás Janciga; Martin Kardos; Lubomír Maron; Zsolt Süll (AFRICON, 2013)

Managing digital-system power at the system level. - Dominik Macko; Katarína Jelemenská (AFRICON, 2013)

Self-managing power management unit. - Dominik Macko; Katarína Jelemenská (DDECS, 2014)

Power-efficient power-management logic. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (PATMOS, 2014)

Power-Management Specification in SystemC. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (DDECS, 2015)

Power-management high-level synthesis. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (VLSI-SoC, 2015)

Early-stage verification of power-management specification in low-power systems design. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (DDECS, 2016)

PMS2UPF: An automated transition from ESL to RTL power-intent specification. - Miroslav Siro; Dominik Macko; Katarína Jelemenská (DDECS, 2017)

Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (J. Circuits Syst. Comput., 2017)

Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation. - Dominik Macko; Katarína Jelemenská; Pavel Cicák (Integr., 2018)

Automation of Dynamic Power Management in FPGA-Based Energy-Constrained Systems. - Michal Skuta; Dominik Macko; Katarína Jelemenská (IEEE Access, 2020)