Learning at work - a combination of experience based learning and theoretical education. - Katarina Paulsson; Lisa Sundin (Behav. Inf. Technol., 2000)

Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. - Michael Hübner 001; Katarina Paulsson; Marcus Stitz; Jürgen Becker 001 (ARCS Workshops, 2005)

Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. - Michael Hübner 001; Katarina Paulsson; Jürgen Becker 001 (IPDPS, 2005)

Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. - Jürgen Becker 001; Michael Hübner 001; Katarina Paulsson; Alexander Thomas (ReCoSoC, 2005)

Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (AHS, 2006)

Physical 2D Morphware and Power Reduction Methods for Everyone. - Jürgen Becker 001; Michael Hübner 001; Katarina Paulsson (Dynamically Reconfigurable Architectures, 2006)

Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. - Katarina Paulsson; Michael Hübner 001; Markus Jung; Jürgen Becker 001 (ISVLSI, 2006)

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (SBCCI, 2006)

Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. - Katarina Paulsson; Michael Hübner 001; Günther Auer; Michael Dreschmann; Jürgen Becker 001 (FPL, 2007)

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001; Jean-Marc Philippe; Christian Gamrat (FPL, 2007)

Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. - Katarina Paulsson; Michael Hübner 001; Salih Bayar; Jürgen Becker 001 (ReCoSoC, 2007)

Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (DATE, 2008)

Data path driven waveform-like reconfiguration. - Lars Braun; Katarina Paulsson; Herrmann Krömer; Michael Hübner 001; Jürgen Becker 001 (FPL, 2008)

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (FPL, 2008)

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. - Katarina Paulsson; Ulrich Viereck; Michael Hübner 001; Jürgen Becker 001 (ISVLSI, 2008)

Towards Novel Approaches in Design Automation for FPGA Power Optimization. - Juanjo Noguera; Robert Esser; Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (PATMOS, 2008)

Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (Microprocess. Microsystems, 2009)