Arithmetic built-in self-test for DSP cores. - Katarzyna Radecka; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. - Zeljko Zilic; Katarzyna Radecka (ISSAC, 1999)

Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. - Katarzyna Radecka; Zeljko Zilic (VTS, 2000)

Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. - Katarzyna Radecka; Zeljko Zilic (ICCD, 2001)

Combinational verification by simulations, SAT and BDDs. - Katarzyna Radecka; Zeljko Zilic; Karim Khordoc (ICECS, 2001)

: Identifying redundant gate replacements in verification by error modeling. - Zeljko Zilic; Katarzyna Radecka (ITC, 2001)

Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. - Katarzyna Radecka; Zeljko Zilic (ICCAD, 2002)

The Role of Super-Fast Transforms in Speeding Up Quantum Computations. - Zeljko Zilic; Katarzyna Radecka (ISMVL, 2002)

Identifying Redundant Wire Replacements for Synthesis and Verification. - Katarzyna Radecka; Zeljko Zilic (ASP-DAC/VLSI Design, 2002)

FPGA Emulation of Quantum Circuits. - Ahmed Usman Khalid; Zeljko Zilic; Katarzyna Radecka (ICCD, 2004)

Architectures of Increased Availability Wireless Sensor Network Nodes. - Man Wah Chiang; Zeljko Zilic; Jean-Samuel Chenard; Katarzyna Radecka (ITC, 2004)

Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. - Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Computers, 2004)

Algorithms for Compositions of Arithmetic Transforms and Their Extensions. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2006)

Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2006)

Testing QCA Modular Logic. - Sayeeda Sultana; Shahriar Al-Imam; Katarzyna Radecka (ICECS, 2006)

Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. - Rong Zhang; Zeljko Zilic; Katarzyna Radecka (VTS, 2006)

Reversible circuit technology mapping from non-reversible specifications. - Zeljko Zilic; Katarzyna Radecka; Ali Kazamiphur (DATE, 2007)

Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. - Ali Khazamipour; Katarzyna Radecka (J. Multiple Valued Log. Soft Comput., 2007)

Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. - Zeljko Zilic; Katarzyna Radecka (IEEE Trans. Computers, 2007)

Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. - Yu Pang; Katarzyna Radecka (DAC, 2008)

Design for Testability of QCA Logic Under Stuck-at-value Fault Model. - Sayeeda Sultana; Shahriar Al-Imam; Katarzyna Radecka (J. Multiple Valued Log. Soft Comput., 2008)

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. - Omid Sarbishei; Yu Pang; Katarzyna Radecka (HLDVT, 2010)

Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. - Omid Sarbishei; Katarzyna Radecka (ICCAD, 2010)

An efficient method to perform range analysis for DSP circuits. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ICECS, 2010)

Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. - Omid Sarbishei; Katarzyna Radecka (IEEE Symposium on Computer Arithmetic, 2011)

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. - Yu Pang; Katarzyna Radecka; Zeljko Zilic (ASP-DAC, 2011)

Positive Davio-based synthesis algorithm for reversible logic. - Yu Pang; Shaoquan Wang; Zhilong He; Jinzhao Lin; Sayeeda Sultana; Katarzyna Radecka (ICCD, 2011)

A study on relating redundancy removal in classical circuits to reversible mapping. - Sayeeda Sultana; Katarzyna Radecka; Yu Pang (ICCD, 2011)

Reversible implementation of square-root circuit. - Sayeeda Sultana; Katarzyna Radecka (ICECS, 2011)

A novel method of synthesizing reversible logic. - Yu Pang; Jinzhao Lin; Sayeeda Sultana; Katarzyna Radecka (ISCAS, 2011)

An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. - Yu Pang; Katarzyna Radecka (ISCAS, 2011)

Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. - Omid Sarbishei; Katarzyna Radecka (ISCAS, 2011)

Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. - Sayeeda Sultana; Katarzyna Radecka (ISMVL, 2011)

Fault tolerant glucose sensor readout and recalibration. - Zeljko Zilic; Katarzyna Radecka (Wireless Health, 2011)

Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. - Omid Sarbishei; Katarzyna Radecka (ASP-DAC, 2012)

MSE minimization and fault-tolerant data fusion for multi-sensor systems. - Atena Roshan Fekr; Majid Janidarmian; Omid Sarbishei; Benjamin Nahill; Katarzyna Radecka; Zeljko Zilic (ICCD, 2012)

Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). - Omid Sarbishei; Katarzyna Radecka (ISCAS, 2012)

Issues in Multi-valued Multi-modal Sensor Fusion. - Majid Janidarmian; Zeljko Zilic; Katarzyna Radecka (ISMVL, 2012)

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. - Omid Sarbishei; Katarzyna Radecka; Zeljko Zilic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

SAR Computation and Channel Modeling of Body Area Network. - Yu Pang; Qian Lei; Jinzhao Lin; Zhiyong Luo; Zhangyong Li; Zeljko Zilic; Katarzyna Radecka (BODYNETS, 2013)

An efficient fault-tolerant sensor fusion algorithm for accelerometers. - Omid Sarbishei; Benjamin Nahill; Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic; Boris Karajica (BSN, 2013)

A minimum MSE sensor fusion algorithm with tolerance to multiple faults. - Omid Sarbishei; Atena Roshan Fekr; Majid Janidarmian; Benjamin Nahill; Katarzyna Radecka (ETS, 2013)

SAT-based reversible gate/wire replacement fault testing. - Sayeeda Sultana; Atena Roshan Fekr; Katarzyna Radecka (MWSCAS, 2013)

Testing reversible adder/subtractor for missing control points. - Sayeeda Sultana; Katarzyna Radecka (MWSCAS, 2013)

On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. - Omid Sarbishei; Katarzyna Radecka (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (BIBE, 2014)

Multi-sensor blind recalibration in mHealth applications. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IHTC, 2014)

Affordable erehabilitation monitoring platform. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (IHTC, 2014)

Development of a Remote Monitoring System for Respiratory Analysis. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IoT360 (1), 2014)

Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2014)

Automated diagnosis of knee pathology using sensory data. - Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2014)

A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. - Omid Sarbishei; Katarzyna Radecka; Zeljko Zilic (NEWCAS, 2014)

A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (Sensors, 2014)

ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths. - Yu Pang; Yafeng Yan; Jinzhao Lin; Guoquan Li; Huawei Huang; Lei Shi; Katarzyna Radecka (J. Circuits Syst. Comput., 2015)

Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (Netw. Model. Anal. Health Informatics Bioinform., 2015)

Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. - Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (IEEE J. Biomed. Health Informatics, 2015)

Haptic feedback and human performance in a wearable sensor system. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (BHI, 2016)

Respiration Disorders Classification With Informative Features for m-Health Applications. - Atena Roshan Fekr; Majid Janidarmian; Katarzyna Radecka; Zeljko Zilic (IEEE J. Biomed. Health Informatics, 2016)

Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2017)

A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (MobiHealth, 2017)

A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (Sensors, 2017)

Exploring Better Food Detection via Transfer Learning. - Jianing Sun; Katarzyna Radecka; Zeljko Zilic (MVA, 2019)

FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. - Jianing Sun; Katarzyna Radecka; Zeljko Zilic (CoRR, 2019)

Wearable Vibrotactile System as an Assistive Technology Solution. - Majid Janidarmian; Atena Roshan Fekr; Katarzyna Radecka; Zeljko Zilic (Mob. Networks Appl., 2022)