A Comparison of MVDR and LCMV Beamformers' Floating Point Implementations on FPGAs. - Siavash Amin-Nejad; Tayyebeh Asgari Gashteroodkhani; Katayoon Basharkhah (Wirel. Pers. Commun., 2018)

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. - Rezgar Sadeghi; Nooshin Nosrati; Katayoon Basharkhah; Zainalabedin Navabi (ETS, 2019)

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. - Samira Ahmadi Farsani; Katayoon Basharkhah; Amin Mohaghegh; Zainalabedin Navabi (EWDTS, 2019)

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. - Nooshin Nosrati; Katayoon Basharkhah; Rezgar Sadeghi; Carna Zivkovic; Christoph Grimm 001; Zainalabedin Navabi (EWDTS, 2019)

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Rezgar Sadeghi; Jaan Raik; Maksim Jenihhin; Zainalabedin Navabi (EWDTS, 2019)

An ESL Environment for Modeling Electrical Interconnect Faults. - Nooshin Nosrati; Katayoon Basharkhah; Rezgar Sadeghi; Zainalabedin Navabi (ISVLSI, 2019)

Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Maryam Rajabalipanah; Seyedeh Maryam Ghasemi; Zainalabedin Navabi (DDECS, 2020)

Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. - Maryam Rajabalipanah; Seyedeh Maryam Ghasemi; Nooshin Nosrati; Katayoon Basharkhah; Saba Yousefzadeh; Zainalabedin Navabi (DFT, 2020)

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. - Katayoon Basharkhah; Rezgar Sadeghi; Nooshin Nosrati; Zainalabedin Navabi (VTS, 2020)

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. - Nooshin Nosrati; Katayoon Basharkhah; Hanieh Totonchi Asl; Zahra Mahdavi; Zainalabedin Navabi (DTIS, 2021)

Online Testing of a Row-Stationary Convolution Accelerator. - Mohammad Rasoul Roshanshah; Katayoon Basharkhah; Zainalabedin Navabi (ETS, 2021)

Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. - Katayoon Basharkhah; Raheleh Sadat Mirhashemi; Nooshin Nosrati; Mohammad-Javad Zare; Zainalabedin Navabi (ETS, 2023)

Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. - Katayoon Basharkhah; Zainalabedin Navabi (ISVLSI, 2024)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library. - Amirmahdi Joudi; Negin Safari; Fatemeh Mohammadzadeh; Katayoon Basharkhah; Fatemeh Sheikhshoaei; Zainalabedin Navabi (ETS, 2025)

An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment. - Katayoon Basharkhah; Zahra Hojati; Zainalabedin Navabi (ISVLSI, 2025)