Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs. - Wen-Chieh Chen; S.-H. Chen; Anabela Veloso; Kateryna Serbulova; Geert Hellings; Guido Groeseneken (VLSI Technology and Circuits, 2023)

Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications. - Kateryna Serbulova; Zi-En Qiu; Shih-Hung Chen; Alexander Grill; Kuo-Hsing Kao; Jo De Boeck; Guido Groeseneken (IRPS, 2024)