Noise-aware buffer planning for interconnect-driven floorplanning. - Katherine Shu-Min Li; Yih-Huai Cherng; Yao-Wen Chang (ASP-DAC, 2003)

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2004)

Oscillation ring based interconnect test scheme for SOC. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (ASP-DAC, 2005)

Finite State Machine Synthesis for At-Speed Oscillation Testability. - Katherine Shu-Min Li; Chung-Len Lee 001; Tagin Jiang; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2005)

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. - Sying-Jyan Wang; Kuo-Lin Peng; Katherine Shu-Min Li (ATS, 2006)

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. - Katherine Shu-Min Li; Chauchin Su; Yao-Wen Chang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. - Sying-Jyan Wang; Xin-Long Li; Katherine Shu-Min Li (ATS, 2007)

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. - Sying-Jyan Wang; Po-Chang Tsai; Hung-Ming Weng; Katherine Shu-Min Li (ATS, 2007)

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. - Sying-Jyan Wang; Yan-Ting Chen; Katherine Shu-Min Li (ISCAS, 2007)

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2007)

Multilevel Full-Chip Routing With Testability and Yield Enhancement. - Katherine Shu-Min Li; Yao-Wen Chang; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization. - Katherine Shu-Min Li; Jr-Yang Huang (ATS, 2008)

Design and analysis of skewed-distribution scan chain partition for improved test data compression. - Sying-Jyan Wang; Shih-Cheng Chen; Katherine Shu-Min Li (ISCAS, 2008)

Layout-aware scan chain reorder for launch-off-shift transition test coverage. - Sying-Jyan Wang; Kuo-Lin Peng; Kuang-Cyun Hsiao; Katherine Shu-Min Li (ACM Trans. Design Autom. Electr. Syst., 2008)

Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. - Yu-Wei Yang; Katherine Shu-Min Li (ASP-DAC, 2009)

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint. - Katherine Shu-Min Li; Yu-Chen Hung; Jr-Yang Huang (Asian Test Symposium, 2009)

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. - Katherine Shu-Min Li; Yi-Yu Liao; Yuo-Wen Liu; Jr-Yang Huang (Asian Test Symposium, 2009)

Level Converting Scan Flip-flops. - Katherine Shu-Min Li; Ming-Hua Hsieh; Sying-Jyan Wang (ISCAS, 2009)

Low Peak Power ATPG for n-Detection Test. - Sying-Jyan Wang; Kuo-Lin Fu; Katherine Shu-Min Li (ISCAS, 2009)

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. - Sying-Jyan Wang; Katherine Shu-Min Li; Shih-Cheng Chen; Huai-Yan Shiu; Yun-Lung Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure. - Chih-Yun Pai; Katherine Shu-Min Li (Asian Test Symposium, 2010)

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint. - Katherine Shu-Min Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Unified Interconnects Testing Scheme for 3D Integrated Circuits. - Chih-Yun Pai; Ruei-Ting Gu; Bo-Chuan Cheng; Liang-Bi Chen; Katherine Shu-Min Li (Asian Test Symposium, 2011)

Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits. - Yi-Xue Zheng; Po-Ping Kan; Liang-Bi Chen; Kai-Yang Hsieh; Bo-Chuan Cheng; Katherine Shu-Min Li (SoCC, 2011)

Synthesizing Multiple Scan Trees to Optimize Test Application Time. - Katherine Shu-Min Li; Jr-Yang Huang (IEEE Des. Test Comput., 2011)

Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip. - Katherine Shu-Min Li; Chih-Yun Pai; Liang-Bi Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

De Bruijn graph-based communication modeling for fault tolerance in smart grids. - Bo-Chuan Cheng; Katherine Shu-Min Li; Sying-Jyan Wang (APCCAS, 2012)

Intelligent home management in the smart grids. - Meng-Kang Chiang; Katherine Shu-Min Li (APCCAS, 2012)

Low-power delay test architecture for pre-bond test. - Sying-Jyan Wang; Han-Hsuan Hsu; Katherine Shu-Min Li (ISCAS, 2012)

Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs. - Katherine Shu-Min Li; Yi-Yu Liao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. - Yingchieh Ho; Katherine Shu-Min Li; Sying-Jyan Wang (Asian Test Symposium, 2013)

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. - Katherine Shu-Min Li; Cheng-You Ho; Ruei-Ting Gu; Sying-Jyan Wang; Yingchieh Ho; Jiun-Jie Huang; Bo-Chuan Cheng; An-Ting Liu (Asian Test Symposium, 2013)

Synthesis of 3D clock tree with pre-bond testability. - Sying-Jyan Wang; Cheng-Hao Lin; Katherine Shu-Min Li (ISCAS, 2013)

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. - Yingchieh Ho; Katherine Shu-Min Li; Sying-Jyan Wang (VLSI-DAT, 2013)

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. - Sying-Jyan Wang; Yu-Siao Chen; Katherine Shu-Min Li (VLSI-DAT, 2013)

Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning. - Katherine Shu-Min Li; Yingchieh Ho; Liang-Bi Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

CusNoC: Fast Full-Chip Custom NoC Generation. - Katherine Shu-Min Li (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Oscillation and Transition Tests for Synchronous Sequential Circuits. - Katherine Shu-Min Li (IEEE Trans. Very Large Scale Integr. Syst., 2013)

IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test. - Katherine Shu-Min Li; Yi-Yu Liao (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Optimized Pre-bond Test Methodology for Silicon Interposer Testing. - Katherine Shu-Min Li; Sying-Jyan Wang; Jia-Lin Wu; Cheng-You Ho; Yingchieh Ho; Ruei-Ting Gu; Bo-Chuan Cheng (ATS, 2014)

Improving Output Compaction Efficiency with High Observability Scan Chains. - Sying-Jyan Wang; Che-Wei Kao; Katherine Shu-Min Li (ATS, 2014)

A Hybrid Multi-functions Digital Public Address System with Earthquake Early Warning. - Chung Heng Chuang; Tsung-Hsing Lin; Liang-Bi Chen; Tung-Lin Lee; Chaio Hsuan Chuang; Katherine Shu-Min Li; Chih-Lin Hung; Chao-Wen Wu (IIH-MSP, 2014)

Fast and accurate statistical static timing analysis. - Sying-Jyan Wang; Tsung-Huei Tzeng; Katherine Shu-Min Li (ISCAS, 2014)

An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip. - Katherine Shu-Min Li; Yingchieh Ho; Yu-Wei Yang; Liang-Bi Chen (IEICE Trans. Inf. Syst., 2014)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. - Hsin-Chen Chen; Cheng-Rong Wu; Katherine Shu-Min Li; Kuen-Jong Lee (DATE, 2015)

An intelligent vehicular telematics platform for vehicle driving safety supporting system. - Liang-Bi Chen; Hong-Yuan Li; Wan-Jung Chang; Jing-Jou Tang; Katherine Shu-Min Li (ICCVE, 2015)

Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ASP-DAC, 2016)

Side-Channel Attack on Flipped Scan Chains. - Sying-Jyan Wang; Ting-Jui Choi; Katherine Shu-Min Li (ATS, 2016)

A wearable-glasses-based drowsiness-fatigue-detection system for improving road safety. - Liang-Bi Chen; Wan-Jung Chang; Jian-Ping Su; Ji-Yi Ciou; Yi-Jhan Ciou; Cheng-Chin Kuo; Katherine Shu-Min Li (GCCE, 2016)

Test generation for combinational hardware Trojans. - Sying-Jyan Wang; Jhih-Yu Wei; Shih-Heng Huang; Katherine Shu-Min Li (AsianHOST, 2016)

Design and development of an extensible multi-protocol automotive gateway. - Hong-Yuan Li; Liang-Bi Chen; Wan-Jung Chang; Jing-Jou Tang; Katherine Shu-Min Li (ICCE-TW, 2016)

An adaptive residential energy management scheme in the smart home. - Liang-Bi Chen; Meng-Kang Chiang; Chia-Lin Liu; Katherine Shu-Min Li; Jing-Jou Tang (ICCE, 2016)

An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks. - Liang-Bi Chen; Bo-Chuan Cheng; You-Chiun Wang; Katherine Shu-Min Li; Jing-Jou Tang (ICCE, 2016)

A real-time mobile emergency assistance system for helping deaf-mute people/elderly singletons. - Liang-Bi Chen; Chia-Wei Tsai; Wan-Jung Chang; Yuh-Ming Cheng; Katherine Shu-Min Li (ICCE, 2016)

Test and diagnosis of paper-based microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (VTS, 2016)

WristEye: Wrist-Wearable Devices and a System for Supporting Elderly Computer Learners. - Liang-Bi Chen; Hong-Yuan Li; Wan-Jung Chang; Jing-Jou Tang; Katherine Shu-Min Li (IEEE Access, 2016)

A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan. - Liang-Bi Chen; Wan-Jung Chang; Kuen-Min Lee; Chi-Wei Huang; Katherine Shu-Min Li (IEICE Trans. Inf. Syst., 2016)

Testing Clock Distribution Networks. - Sying-Jyan Wang; Hsiang-Hsueh Chen; Chin-Hung Lien; Katherine Shu-Min Li (ATS, 2017)

Design-for-testability for paper-based digital microfluidic biochips. - Jain-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (DFT, 2017)

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. - Katherine Shu-Min Li; Sying-Jyan Wang; Ruei-Ting Gu; Bo-Chuan Cheng (IEEE Des. Test, 2017)

2016 IEEE Education Society Awards, 2016 Frontiers in Education Conference Awards, and Selected IEEE Awards. - Edwin C. Jones; Kathleen E. Wage; Sanjit A. Seshia; Susan M. Lord; Michael E. Auer; Lance C. Pérez; Katherine Shu-Min Li; S. L. Krishna Priya; Sasha Nikolic; Francisco Arcega; Richard A. Layton; Matthew W. Ohland; et al. (IEEE Trans. Educ., 2017)

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. - Katherine Shu-Min Li; Sying-Jyan Wang (ACM Trans. Design Autom. Electr. Syst., 2017)

Digital Rights Management for Paper-Based Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ATS, 2018)

Register PUF with No Power-Up Restrictions. - Sying-Jyan Wang; Chin-Hung Lien; Katherine Shu-Min Li (ISCAS, 2018)

SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. - Jia-Lin Wu; Katherine Shu-Min Li; Jain-De Li; Sying-Jyan Wang; Tsung-Yi Ho (VLSI-DAT, 2018)

Adversarial Attack against Modeling Attack on PUFs. - Sying-Jyan Wang; Yu-Shen Chen; Katherine Shu-Min Li (DAC, 2019)

TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. - Andrew Yi-Ann Huang; Katherine Shu-Min Li; Cheng-Yen Tsai; Ken Chau-Cheung Cheng; Sying-Jyan Wang; Xu-Hao Jiang; Leon Chou; Chen-Shiun Lee (ITC, 2019)

Exploiting distribution of unknown values in test responses to optimize test output compactors. - Sying-Jyan Wang; Kuan-Ting Yeh; Katherine Shu-Min Li (Integr., 2019)

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. - Jian-De Li; Chun-Hao Kuo; Guan-Ruei Lu; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho; Hung-Ming Chen; Shiyan Hu 001 (Microelectron. J., 2019)

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Andrew Yi-Ann Huang; Ji-Wei Li; Leon Li-Yang Chen; Nova Cheng-Yen Tsai; Sying-Jyan Wang; Chen-Shiun Lee; Leon Chou; Peter Yi-Yu Liao; Hsing-Chung Liang; Jwu E. Chen (DATE, 2020)

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. - Katherine Shu-Min Li; Peter Yi-Yu Liao; Leon Chou; Ken Chau-Cheung Cheng; Andrew Yi-Ann Huang; Sying-Jyan Wang; Gus Chang-Hung Han (ETS, 2020)

Feature Selection for Malicious Traffic Detection with Machine Learning. - Sying-Jyan Wang; Cheng Xuan Cai; Yen-Wen Tseng; Katherine Shu-Min Li (ICS, 2020)

Watermarking for Paper-Based Digital Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ITC-Asia, 2020)

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. - Leon Li-Yang Chen; Katherine Shu-Min Li; Ken Chau-Cheung Cheng; Sying-Jyan Wang; Andrew Yi-Ann Huang; Leon Chou; Nova Cheng-Yen Tsai; Chen-Shiun Lee (ITC, 2020)

Innovative Practice on Wafer Test Innovations. - Dyi-Chung Hu; Hirohito Hashimoto; Li-Fong Tseng; Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Sean Y.-S. Chen; Jwu E. Chen; Clark Liu; Andrew Yi-Ann Huang (VTS, 2020)

Using Tree Structure to Mine High Temporal Fuzzy Utility Itemsets. - Tzung-Pei Hong; Cheng-Yu Lin; Wei-Ming Huang; Katherine Shu-Min Li; Shyue-Liang Leon Wang; Jerry Chun-Wei Lin (IEEE Access, 2020)

Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. - Fang-Chi Wu; Jian-De Li; Katherine Shu-Min Li; Sying-Jyan Wang; Tsung-Yi Ho (DATE, 2021)

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. - Katherine Shu-Min Li; Leon Li-Yang Chen; Ken Chau-Cheung Cheng; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Nova Cheng-Yen Tsai; Leon Chou; Gus Chang-Hung Han; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ETS, 2021)

Integrated Scratch Marker for Wafer Defect Diagnosis. - Katherine Shu-Min Li; Leon Li-Yang Chen; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng (ITC-Asia, 2021)

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. - Leon Li-Yang Chen; Katherine Shu-Min Li; Xu-Hao Jiang; Sying-Jyan Wang; Andrew Yi-Ann Huang; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ITC, 2021)

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. - Peter Yi-Yu Liao; Katherine Shu-Min Li; Leon Li-Yang Chen; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng; Nova Cheng-Yen Tsai; Leon Chou (ITC, 2021)

Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs. - Sying-Jyan Wang; Tzu-Heng Chang; Katherine Shu-Min Li (VLSI-DAT, 2021)

Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning. - Sying-Jyan Wang; Yu-Sheng Chen; Katherine Shu-Min Li (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ASP-DAC, 2022)

Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication. - Sying-Jyan Wang; Katherine Shu-Min Li; Chen-Yeh Lin; Song-Kong Chong (ATS, 2022)

Trojan Insertions of Fully Programmable Valve Arrays. - Nadun Sinhabahu; Jian-De Li; Katherine Shu-Min Li; Sying-Jyan Wang; Tsung-Yi Ho (ETS, 2022)

Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Andrew Yi-Ann Huang; Chen-Shiun Lee; Leon Li-Yang Chen; Peter Yi-Yu Liao; Nova Cheng-Yen Tsai (ITC, 2022)

Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. - Nadun Sinhabahu; Katherine Shu-Min Li; Jian-De Li; J. R. Wang; Sying-Jyan Wang (ITC, 2022)

Improving IJTAG Test Efficiency and Security. - Sying-Jyan Wang; Yen-Chang Shih; Katherine Shu-Min Li; Chen-Yeh Lin; Song-Kong Chong (VLSI-DAT, 2022)

Effective Natural Language Processing and Interpretable Machine Learning for Structuring CT Liver-Tumor Reports. - Yi-Hsuan Chuang; Ja-Hwung Su; Ding-Hong Han; Yi-Wen Liao; Yeong-Chyi Lee; Yu-Fan Cheng; Tzung-Pei Hong; Katherine Shu-Min Li; Hsin-You Ou; Yi Lu; Chih-Chi Wang (IEEE Access, 2022)

Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. - Nadun Sinhabahu; Katherine Shu-Min Li; Sying-Jyan Wang; J. R. Wang; Matt Ho (ITC, 2023)

Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (Integr., 2023)

Federated Erasable-Itemset Mining with Quasi-Erasable Itemsets. - Tzung-Pei Hong; Meng-Jui Kuo; Chun-Hao Chen; Katherine Shu-Min Li (ACIIDS (1), 2024)

A Federated Mining Framework for Complete Erasable Itemsets. - Tzung-Pei Hong; Meng-Jui Kuo; Chun-Hao Chen; Katherine Shu-Min Li (IEEE Big Data, 2024)

Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips. - Jian-De Li; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho (ACM Trans. Design Autom. Electr. Syst., 2024)

Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. - Katherine Shu-Min Li; Fang-Chi Wu; Jian-De Li; Sying-Jyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Privacy Preserving Based on SHA Encryption and Cluster Analysis in Federated Frequent Itemset Mining. - Tzung-Pei Hong; Chi-Chien Chen; Chun-Hao Chen; Katherine Shu-Min Li (ACIIDS (1), 2025)

Masking Based Protection Mechanism for Ascon against CPA Attack. - Sying-Jyan Wang; Ho Lam Cheung; Katherine Shu-Min Li (ISCAS, 2025)

Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications. - Sying-Jyan Wang; Gong-Chi Wang; Chi-Yun Chen; Katherine Shu-Min Li (ISCAS, 2025)