Yield Analysis of Logic Circuits. - Davide Appello; Alessandra Fudoli; Katia Giarda; Emil Gizdarski; Ben Mathew; Vincenzo Tancorre (VTS, 2004)

Understanding Yield Losses in Logic Circuits. - Davide Appello; Alessandra Fudoli; Katia Giarda; Vincenzo Tancorre; Emil Gizdarski; Ben Mathew (IEEE Des. Test Comput., 2004)