A 70 nm 16 Gb 16-Level-Cell NAND flash Memory. - Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; et al. (IEEE J. Solid State Circuits, 2008)

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. - Cuong Trinh; Noboru Shibata; Takeshi Nakano; Mikio Ogawa; Jumpei Sato; Yoshikazu Takeyama; Katsuaki Isobe; Binh Le; Farookh Moogat; Nima Mokhlesi; Kenji Kozakai; Patrick Hong; et al. (ISSCC, 2009)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface. - Kazushige Kanda; Noboru Shibata; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Naoaki Kanagawa; Yasuyuki Kajitani; Takeshi Ogawa; et al. (IEEE J. Solid State Circuits, 2013)

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. - Chang Hua Siau; Kwang-Ho Kim; Seungpil Lee; Katsuaki Isobe; Noboru Shibata; Kapil Verma; Takuya Ariki; Jason Li 001; Jong Yuh; Anirudh Amarnath; Qui Nguyen; Ohwon Kwon; et al. (ISSCC, 2019)

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure. - Hiroshi Maejima; Katsuaki Isobe; N. Okada; Masaki Unno; T. Hashimoto; Tetsuaki Utsumi; T. Hisada; K. Maruyama; Toshiyuki Kouchi; T. Kotani; Hitoshi Shiga; O. Kwon; et al. (IMW, 2025)