A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2003)

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (ISMVL, 2004)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. - Hiroshi Inokawa; Yasuo Takahashi; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2004)

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Hiroshi Inokawa; Tatsuo Higuchi 001; Yasuo Takahashi (ISMVL, 2005)

Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2005)

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Katsuhiko Nishiguchi; Yasuo Takahashi (ISMVL, 2006)

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. - Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2007)

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (J. Multiple Valued Log. Soft Comput., 2007)

Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. - Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2007)

High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. - Yuki Watanabe; Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2008)

Phase-based alignment of two signals having partially overlapped spectra. - Albert Tumewu; Kazuyuki Miyazawa; Takafumi Aoki; Takahiro J. Yamaguchi; Katsuhiko Degawa; Takayuki Akita (ICASSP, 2009)

Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. - Naofumi Homma; Yuki Watanabe; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2009)

An equivalent-time and clocked approach for continuous-time quantization. - Takahiro J. Yamaguchi; Mohamed Abbas; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Satoshi Komatsu; Kunihiro Asada (ISCAS, 2011)

Application of a continuous-time level crossing quantization method for timing noise measurements. - Takahiro J. Yamaguchi; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Kunihiro Asada; Mohamed Abbas; Satoshi Komatsu (ITC, 2011)

A new method for measuring alias-free aperture jitter in an ADC output. - Takahiro J. Yamaguchi; Katsuhiko Degawa; Masayuki Kawabata; Masahiro Ishida; Koichiro Uekusa; Mani Soma (ITC, 2015)