An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

BiCMOS circuit technology for high-speed DRAMs. - Shigeyoshi Watanabe; Koji Sakui; Tsuneaki Fuse; Takahiko Hara; Seiichi Aritome; Katsuhiko Hieda (IEEE J. Solid State Circuits, 1993)