Design of a Multiple-Valued VLSI Processor for Digital Control. - Katsuhiko Shimabukuro; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits. - Katsuhiko Shimabukuro; Chotei Zukeran (ISMVL, 1998)

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. - Takahiro Hanyu; Michitaka Kameyama; Katsuhiko Shimabukuro; Chotei Zukeran (ISMVL, 2001)

Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution. - Mitsunaga Kinjo; Katsuhiko Shimabukuro (ISMVL, 2011)

Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic. - Katsuhiko Shimabukuro; Michitaka Kameyama (ISMVL, 2017)

QUBO Model Formulation Based on Petri Net Behavioral Description for Combinatorial Optimization Problems. - Keisuke Tokuhira; Morikazu Nakamura; Mitsunaga Kinjo; Katsuhiko Shimabukuro (ICO, 2022)