Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. - Kentaro Kawakami; Takeshi Shiro; Hironobu Yamasaki; Katsuhiro Yoda; Hiroaki Fujimoto; Kenichi Kawasaki; Yasuhiro Watanabe (ISQED, 2013)

STRAIGHT: Hazardless Processor Architecture Without Register Renaming. - Hidetsugu Irie; Toru Koizumi 001; Akifumi Fukuda; Seiya Akaki; Satoshi Nakae; Yutaro Bessho; Ryota Shioya; Takahiro Notsu; Katsuhiro Yoda; Teruo Ishihara; Shuichi Sakai (MICRO, 2018)

Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management. - Hisakatsu Yamaguchi; Makiko Ito; Katsuhiro Yoda; Atsushi Ike (DATE, 2021)

Out-of-Step Pipeline for Gather/Scatter Instructions. - Yi Ge; Katsuhiro Yoda; Makiko Ito; Toshiyuki Ichiba; Takahide Yoshikawa; Ryota Shioya; Masahiro Goshima (DATE, 2023)