A method of constructing large-scale program processor for 8-bit system utilizing memory mapping feature. - Tatsuo Tsuji; Kazuto Kontani; Katsumasa Watanabe; Mitsuaki Sumiya (Syst. Comput. Jpn., 1987)

Structured FORTRAN Preprocessors Generating Optimized Output. - Tatsuo Tsuji; Katsumasa Watanabe; Athushi Ikehata (Softw. Pract. Exp., 1988)

A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. - Shinji Kimura; Yasufumi Itou; Makoto Hirao; Katsumasa Watanabe; Mitsuteru Yukishita; Akira Nagoya (CODES, 1997)

Waiting false path analysis of sequential logic circuits for performance optimization. - Kazuhiro Nakamura; Kazuyoshi Takagi; Shinji Kimura; Katsumasa Watanabe (ICCAD, 1998)

An application specific Java processor with reconfigurabilities. - Shinji Kimura; Hiroyuki Kida; Kazuyoshi Takagi; Tatsumori Abematsu; Katsumasa Watanabe (ASP-DAC, 2000)

Multi-clock path analysis using propositional satisfiability. - Kazuhiro Nakamura; Shinji Maruoka; Shinji Kimura; Katsumasa Watanabe (ASP-DAC, 2000)

A real-time 64-monosyllable recognition LSI with learning mechanism. - Kazuhiro Nakamura; Qiang Zhu 008; Shinji Maruoka; Takashi Horiyama; Shinji Kimura; Katsumasa Watanabe (ASP-DAC, 2001)

Speech recognition chip for monosyllables. - Kazuhiro Nakamura; Qiang Zhu 008; Shinji Maruoka; Takashi Horiyama; Shinji Kimura; Katsumasa Watanabe (ASP-DAC, 2001)

Look Up Table Compaction Based on Folding of Logic Functions. - Shinji Kimura; Atsushi Ishii; Takashi Horiyama; Masaki Nakanishi; Hirotsugu Kajihara; Katsumasa Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. - Nobuhiro Doi; Takashi Horiyama; Masaki Nakanishi; Shinji Kimura; Katsumasa Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Event-oriented computing with reconfigurable platform. - Mitsuru Tomono; Masaki Nakanishi; Katsumasa Watanabe; Shigeru Yamashita (ASP-DAC, 2005)

Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. - Nobuo Nakai; Masaki Nakanishi; Shigeru Yamashita; Katsumasa Watanabe (ERSA, 2005)

A New Approach to Online FPGA Placement. - Mitsuru Tomono; Masaki Nakanishi; Shigeru Yamashita; Kazuo Nakajima; Katsumasa Watanabe (CISS, 2006)

Robust Quantum Algorithms with epsilon-Biased Oracles. - Tomoya Suzuki; Shigeru Yamashita; Masaki Nakanishi; Katsumasa Watanabe (COCOON, 2006)

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. - Mitsuru Tomono; Masaki Nakanishi; Shigeru Yamashita; Kazuo Nakajima; Katsumasa Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. - Tomoya Suzuki; Shigeru Yamashita; Masaki Nakanishi; Katsumasa Watanabe (IEICE Trans. Inf. Syst., 2007)