Analysis of coupling noise between adjacent bit lines in megabit DRAMs. - Yasuhiro Konishi; Masaki Kumanoya; Hiroyuki Yamasaki; Katsumi Dosaka; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1989)

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. - Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Inoue; Masaki Kumanoya; Youichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1990)

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme. - Katsumi Dosaka; Yasuhiro Konishi; Kouji Hayano; Katsumitsu Himukashi; Akira Yamazaki; Hisashi Iwamoto; Masaki Kumanoya; Hisanori Hamano; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1992)

A 90-MHz 16-Mb system integrated memory with direct interface to CPU. - Katsumi Dosaka; Akira Yamazaki; Naoya Watanabe; Hideaki Abe; Jun Ohtani; Toshiyuki Ogawa; Kazunori Ishihara; Masaki Kumanoya (IEEE J. Solid State Circuits, 1996)

Design methodology of the embedded DRAM with the virtual socket architecture. - Mitsuya Kinoshita; Tadaaki Yamauchi; Teruhiko Amano; Katsumi Dosaka; Kenshin Arimoto (CICC, 2000)

Test cost reduction by at-speed BISR for embedded DRAMs. - Yoshihiro Nagura; Michael Mullins; Anthony Sauvageau; Yoshinoro Fujiwara; Katsuya Furue; Ryuji Ohmura; Tatsunori Komoike; Takenori Okitaka; Tetsushi Tanizaki; Katsumi Dosaka; Kazutami Arimoto; Yukiyoshi Koda; et al. (ITC, 2001)

Design methodology of embedded DRAM with virtual-socket architecture. - Tadaaki Yamauchi; Mitsuya Kinoshita; Teruhiko Amano; Katsumi Dosaka; Kazutami Arimoto; Hideyuki Ozaki; Michihiro Yamada; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2001)

A capacitorless twin-transistor random access memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (CICC, 2005)

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. - Hideyuki Noda; Katsumi Dosaka; Fukashi Morishita; Kazutami Arimoto (CICC, 2005)

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. - Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Tetsushi Tanizaki; Takashi Ipposhi; Katsumi Dosaka (CICC, 2006)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Katsumi Dosaka; Hiroki Shimano; Takashi Ipposhi (IEEE J. Solid State Circuits, 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2009)

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications. - Katsumi Dosaka; Daisuke Ogawa; Takahito Kusumoto; Masayuki Miyama; Yoshio Matsuda (IEICE Trans. Electron., 2010)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)