A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads. - Fumio Miyaji; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Takashi Emori; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1989)

A multibit test trigger circuit for megabit SRAMs. - Fumio Miyaji; Takashi Emori; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1990)

A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier. - Katsunori Seno; Kurt Knorpp; Lee-Lean Shu; Naoki Teshima; Hiroki Kihara; Hiroshi Sato; Fumio Miyaji; Minoru Takeda; Masayoshi Sasaki; Yoichi Tomo; Patrick T. Chuang; Kazuyoshi Kobayashi (IEEE J. Solid State Circuits, 1993)

Evaluation of a Low-Power Reconfigurable DSP Architecture. - Arthur Abnous; Katsunori Seno; Yuji Ichikawa; Marlene Wan; Jan M. Rabaey (IPPS/SPDP Workshops, 1998)

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor. - Takahiro Seki; Satoshi Akui; Katsunori Seno; Masakatsu Nakai; Tetsumasa Meguro; Tetsuo Kondo; Akihiko Hashiguchi; Hirokazu Kawahara; Kazuo Kumano; Masayuki Shimura (IEICE Trans. Electron., 2005)