A new pipelined architecture of the LMS algorithm without degradation of convergence characteristics. - Katsushige Matsubara; Kiyoshi Nishikawa; Hitoshi Kiya (ICASSP, 1997)

71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding. - Chi Lan Phuong Nguyen; My Phi Ngoc Nguyen; Hung Van Cao; Katsushige Matsubara; Keisuke Matsumoto; Seiji Mochizuki; Kenichi Iwata (ICICDT, 2016)

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (ISSCC, 2016)

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Kazuaki Terashima; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (ISSCC, 2021)

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (IEEE J. Solid State Circuits, 2022)