A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. - Katsutaka Kimura; Takeshi Sakata; Kiyoo Itoh 001; Toru Kaga; Takashi Nishida; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1991)

A single 1.5-V digital chip for a 106 synapse neural network. - Takao Watanabe; Katsutaka Kimura; Masakazu Aoki; Takeshi Sakata; Kiyoo Ito (IEEE Trans. Neural Networks, 1993)

High reliability electron-ejection method for high density flash memories. - Takayuki Kawahara; Naoki Miyamoto; Syun-ichi Saeki; Yusuke Jyouno; Masataka Kato; Katsutaka Kimura (IEEE J. Solid State Circuits, 1995)

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. - Takayuki Kawahara; Takashi Kobayashi 002; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; T. Adachi; Masataka Kato; Akihiko Sato; J. Yugami; Hitoshi Kume; Katsutaka Kimura (IEEE J. Solid State Circuits, 1996)

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. - Hiroki Fujisawa; Takeshi Sakata; Tomonori Sekiguchi; Osamu Nagashima; Katsutaka Kimura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 1997)

20-Mb/s erase/record flash memory by asymmetrical operation. - Takayuki Kawahara; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; Katsutaka Kimura (IEEE J. Solid State Circuits, 1998)

Internal voltage generator for low voltage, quarter-micrometer flash memories. - Takayuki Kawahara; Syun-ichi Saeki; Yusuke Jyouno; Naoki Miyamoto; Takashi Kobayashi 002; Katsutaka Kimura (IEEE J. Solid State Circuits, 1998)

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. - Hitoshi Tanaka; Masakazu Aoki; Takeshi Sakata; Shin'ichiro Kimura; Narumi Sakashita; Hideto Hidaka; Tadashi Tachibana; Katsutaka Kimura (IEEE J. Solid State Circuits, 1999)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A low-impedance open-bitline array for multigigabit DRAM. - Tomonori Sekiguchi; Kiyoo Itoh 001; Tsugio Takahashi; Masahiro Sugaya; Hiroki Fujisawa; Masayuki Nakamura; Kazuhiko Kajigaya; Katsutaka Kimura (IEEE J. Solid State Circuits, 2002)