Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. - Junso Pak; Masahiro Aoyagi; Katsuya Kikuchi; Joungho Kim (IEICE Trans. Electron., 2006)

Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. - Yasuhiro Yamaji; Tokihiko Yokoshima; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (IEICE Electron. Express, 2008)

Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. - Katsuya Kikuchi; Koichi Takemura; Chihiro Ueda; Osamu Shimada; Toshio Gomyo; Yukiharu Takeuchi; Toshikazu Okubo; Kazuhiro Baba; Masahiro Aoyagi; Toshio Sudo; Kanji Otsuka (3DIC, 2009)

SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. - Koichi Takemura; Katsuya Kikuchi; Chihiro Ueda; Kazuhiro Baba; Masahiro Aoyagi; Kanji Otsuka (3DIC, 2009)

Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. - Fumiki Kato; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (3DIC, 2011)

PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. - Katsuya Kikuchi; Chihiro Ueda; Fumiaki Fujii; Yutaka Akiyama; Naoya Watanabe; Yasuhiro Kitamura; Toshio Gomyo; Toshikazu Okubo; Tetsuya Koyama; Tadashi Kamada; Masahiro Aoyagi; Kanji Otsuka (3DIC, 2011)

COOL interconnect low power interconnection technology for scalable 3D LSI design. - Marco Chacin; Hiroyuki Uchida; Michiya Hagimoto; Takashi Miyazaki; Takeshi Ohkawa; Rimon Ikeno; Yukoh Matsumoto; Fumito Imura; Motohiro Suzuki; Katsuya Kikuchi; Hiroshi Nakagawa; Masahiro Aoyagi (COOL Chips, 2011)

New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. - Masahiro Aoyagi; Naoya Watanabe; Motohiro Suzuki; Katsuya Kikuchi; Shunsuke Nemoto; Noriaki Arima; Misaki Ishizuka; Koji Suzuki; Toshio Shiomi (3DIC, 2013)

Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. - Katsuya Kikuchi; Fumiki Kato; Shunsuke Nemoto; Hiroshi Nakagawa; Masahiro Aoyagi; Youtaro Yasu; Kohji Koshiji (3DIC, 2013)

Substrate monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2014)

Analysis of thermal stress distribution for TSV with novel structure. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. - Katsuya Kikuchi; Masahiro Aoyagi; Masaaki Ujiie; Shinya Takayama (3DIC, 2014)

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. - Bui Thanh Tung 001; Xiaojin Cheng; Naoya Watanabe; Fumiki Kato; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2014)

Guard-ring monitoring system for inspecting defects in TSV-based data buses. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2015)

Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. - Tung Thanh Bui 001; Naoya Watanabe; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2015)

Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. - Samson Melamed; Katsuya Kikuchi; Masahiro Aoyagi (3DIC, 2015)

Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. - Samson Melamed; Fumito Imura; Hiroshi Nakagawa; Katsuya Kikuchi; Michiya Hagimoto; Yukoh Matsumoto; Masahiro Aoyagi (Microelectron. J., 2015)

Wet cleaning process for high-yield via-last TSV formation. - Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi; Hidekazu Kikuchi; Azusa Yanagisawa; Akio Nakamura (3DIC, 2016)

Fabrication and stress analysis of annular-trench-isolated TSV. - Wei Feng; Tung Thanh Bui 001; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Validation of TSV thermo-mechanical simulation by stress measurement. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (Microelectron. Reliab., 2016)

Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2016)

Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. - Takeshi Ohkawa; Kanemitsu Ootsu; Takashi Yokota; Katsuya Kikuchi; Masahiro Aoyagi (MCSoC, 2017)

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. - Samson Melamed; Naoya Watanabe; Shunsuke Nemoto; Haruo Shimamoto; Katsuya Kikuchi; Masahiro Aoyagi (Microelectron. Reliab., 2017)

Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. - Yuuki Araga; Kikuchi Katsuya; Masahiro Aoyagi (3DIC, 2019)

Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. - Wei Feng; Naoya Watanabe; Haruo Shimamoto; Masahiro Aoyagi; Katsuya Kikuchi (3DIC, 2019)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

Landside capacitor efficacy among multi-chip-module using Si-interposer. - Yuuki Araga; Ryo Kasai; Daisuke Tanaka; Yoshihide Murakami; Kyoshi Mihara; Kazuo Makida; Hiroki Sonoda; Makoto Nagata; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)

Analysis and evaluation of noise coupling between through-silicon-vias. - Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEICE Electron. Express, 2021)