A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current. - Katsuyuki Sato; Kanehide Kenmizaki; Shoji Kubono; Toshio Mochizuki; Hidetomo Aoyagi; Michitaro Kanamitsu; Soichi Kunito; Hiroyuki Uchida; Yoshihiko Yasu; Atsushi Ogishima; Sho Sano; Hiroshi Kawamoto (IEEE J. Solid State Circuits, 1991)

A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array. - Katsuyuki Sato; Mitsuteru Kobayashi; Hiroyuki Hida; Hideyuki Miyazawa; Yuji Shirai; Kenji Fujita; Toshiyuki Nakao; Masamichi Ishihara (IEEE J. Solid State Circuits, 1992)

A 29-ns 64-Mb DRAM with hierarchical array architecture. - Masayuki Nakamura; Tugio Takahashi; Takesada Akiba; Goro Kitsukawa; Makoto Morino; Toshihiro Sekiguchi; Isamu Asano; Katsuo Komatsuzaki; Yoshitaka Tadaki; Songsu Cho; Kazuhiko Kajigaya; Tadashi Tachibana; et al. (IEEE J. Solid State Circuits, 1996)

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. - Youji Idei; Katsuhiro Shimohigashi; Masakazu Aoki; Hiromasa Noda; Hidetoshi Iwai; Katsuyuki Sato; Tadashi Tachibana (IEEE J. Solid State Circuits, 1998)

Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference. - James D. Warnock; William Bidermann; Albert van der Werf; Katsuyuki Sato (IEEE J. Solid State Circuits, 2007)