On-chip inductance modeling and analysis. - Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Brian Young; Junfeng Wang; David T. Blaauw (DAC, 2000)

On-chip inductance modeling. - David T. Blaauw; Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Junfeng Wang (ACM Great Lakes Symposium on VLSI, 2000)

Fast Analysis and Optimization of Power/Ground Networks. - Haihua Su; Kaushik Gala; Sachin S. Sapatnekar (ICCAD, 2000)

Inductance 101: Analysis and Design Issues. - Kaushik Gala; David T. Blaauw; Junfeng Wang; Vladimir Zolotov; Min Zhao 001 (DAC, 2001)

A precorrected-FFT method for simulating on-chip inductance. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (ICCAD, 2002)

Worst case clock skew under power supply variations. - Min Zhao 001; Kaushik Gala; Vladimir Zolotov; Yuhong Fu; Rajendran Panda; R. Ramkumar; Bhuwan K. Agrawal (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Inductance model and analysis methodology for high-speed on-chip interconnect. - Kaushik Gala; David T. Blaauw; Vladimir Zolotov; Pravin M. Vaidya; Anil Joshi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Statistical delay computation considering spatial correlations. - Aseem Agarwal; David T. Blaauw; Vladimir Zolotov; Savithri Sundareswaran; Min Zhao 001; Kaushik Gala; Rajendran Panda (ASP-DAC, 2003)

Table look-up based compact modeling for on-chip interconnect timing and noise analysis. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (ISCAS (4), 2003)

Fast on-chip inductance simulation using a precorrected-FFT method. - Haitian Hu; David T. Blaauw; Vladimir Zolotov; Kaushik Gala; Min Zhao 001; Rajendran Panda; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Analysis and optimization of structured power/ground networks. - Haihua Su; Kaushik Gala; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)