Test method and scheme for low-power validation in modern SOC integrated circuits. - Bonita Bhaskaran; Amit Sanghani; Kaushik Narayanun; Ayub Abdollahian; Amit Laknaur (VTS, 2016)

A programmable method for low-power scan shift in SoC integrated circuits. - Ran Wang 002; Bonita Bhaskaran; Karthikeyan Natarajan; Ayub Abdollahian; Kaushik Narayanun; Krishnendu Chakrabarty; Amit Sanghani (VTS, 2016)

Test-cost optimization in a scan-compression architecture using support-vector regression. - Zipeng Li; Jonathon E. Colburn; Vinod Pagalone; Kaushik Narayanun; Krishnendu Chakrabarty (VTS, 2017)

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. - Seyed Nima Mozaffari; Bonita Bhaskaran; Kaushik Narayanun; Ayub Abdollahian; Vinod Pagalone; Shantanu Sarangi; Jonathon E. Colburn (ITC, 2019)

Observation Point Insertion Using Deep Learning. - Bonita Bhaskaran; Sanmitra Banerjee; Kaushik Narayanun; Shao-Chun Hung; Seyed Nima Mozaffari Mojaveri; Mengyun Liu; Gang Chen; Tung-Che Liang (ICCAD, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento; Smbat Tonoyan; Ashwin Chintaluri; Animesh Khare; Milind Sonawane; Ashish Kumar; Anitha Kalva; et al. (VTS, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento (IEEE Des. Test, 2023)

A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. - Kunal Jain Mangilal; Mahmut Yilmaz; Vishal Agarwal; Shantanu Sarangi; Kaushik Narayanun (ITC, 2024)