Kaushik Roy
Orcid: 0000-0002-0735-9695Affiliations:
- Purdue University, West Lafayette, IN, USA
According to our database1,
Kaushik Roy
authored at least 863 papers
between 1988 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Artif. Intell., February, 2024
Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2024
EV-Planner: Energy-Efficient Robot Navigation via Event-Based Physics-Guided Neuromorphic Planner.
IEEE Robotics Autom. Lett., 2024
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms.
CoRR, 2024
HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads.
CoRR, 2024
CoRR, 2024
Verifix: Post-Training Correction to Improve Label Noise Robustness with Verified Samples.
CoRR, 2024
CoRR, 2024
CoRR, 2024
HALSIE: Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
2023
Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware.
ACM Comput. Surv., December, 2023
IEEE Trans. Computers, September, 2023
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
Online continual learning with saliency-guided experience replay using tiny episodic memory.
Mach. Vis. Appl., July, 2023
DIET-SNN: A Low-Latency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization.
IEEE Trans. Neural Networks Learn. Syst., June, 2023
IEEE Trans. Artif. Intell., June, 2023
CoRR, 2023
CoRR, 2023
CoRR, 2023
Best of Both Worlds: Hybrid SNN-ANN Architecture for Event-based Optical Flow Estimation.
CoRR, 2023
Homogenizing Non-IID datasets via In-Distribution Knowledge Distillation for Decentralized Learning.
CoRR, 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
DOTIE - Detecting Objects through Temporal Isolation of Events using a Spiking Architecture.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Adaptive-SpikeNet: Event-based Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Live Demonstration: Real-time Event-based Speed Detection using Spiking Neural Networks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Live Demonstration: ANN vs SNN vs Hybrid Architectures for Event-based Real-time Gesture Recognition and Optical Flow Estimation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the 34th British Machine Vision Conference 2023, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Neuro-Ising: Accelerating Large-Scale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Neural Networks, 2022
Event-based Temporally Dense Optical Flow Estimation with Sequential Neural Networks.
CoRR, 2022
Neighborhood Gradient Clustering: An Efficient Decentralized Learning Method for Non-IID Data Distributions.
CoRR, 2022
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks.
CoRR, 2022
TOFU: Towards Obfuscated Federated Updates by Encoding Weight Updates into Gradients from Proxy Data.
CoRR, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Towards Ultra Low Latency Spiking Neural Networks for Vision and Sequential Tasks Using Temporal Pruning.
Proceedings of the Computer Vision - ECCV 2022, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective.
Proceedings of the Approximate Computing, 2022
2021
STDP Based Unsupervised Multimodal Learning With Cross-Modal Processing in Spiking Neural Networks.
IEEE Trans. Emerg. Top. Comput. Intell., 2021
Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Neural Networks, 2021
Neurocomputing, 2021
Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning.
Frontiers Comput. Neurosci., 2021
Quantifying the Brain Predictivity of Artificial Neural Networks With Nonlinear Response Mapping.
Frontiers Comput. Neurosci., 2021
IEEE Des. Test, 2021
One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency.
CoRR, 2021
NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems.
CoRR, 2021
IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks.
CoRR, 2021
Network Compression via Mixed Precision Quantization Using a Multi-Layer Perceptron for the Bit-Width Allocation.
IEEE Access, 2021
SPACE: Structured Compression and Sharing of Representational Space for Continual Learning.
IEEE Access, 2021
Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
Complexity-aware Adaptive Training and Inference for Edge-Cloud Distributed AI Systems.
Proceedings of the 41st IEEE International Conference on Distributed Computing Systems, 2021
DCT-SNN: Using DCT to Distribute Spatial Information over Time for Low-Latency Spiking Neural Networks.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.
IEEE Trans. Computers, 2020
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.
Proc. IEEE, 2020
Neural Networks, 2020
Constructing energy-efficient mixed-precision neural networks through principal component analysis for edge intelligence.
Nat. Mach. Intell., 2020
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators.
IEEE Micro, 2020
Erratum to "CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays".
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
CoRR, 2020
DCT-SNN: Using DCT to Distribute Spatial Information over Time for Learning Low-Latency Spiking Neural Networks.
CoRR, 2020
Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks?
CoRR, 2020
DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks.
CoRR, 2020
CoRR, 2020
RMP-SNNs: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Networks.
CoRR, 2020
CoRR, 2020
Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors.
CoRR, 2020
CoRR, 2020
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing.
IEEE Access, 2020
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.
IEEE Access, 2020
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Energy-Efficient Target Recognition using ReRAM Crossbars for Enabling On-Device Intelligence.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation.
Proceedings of the 8th International Conference on Learning Representations, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-linear Activations.
Proceedings of the Computer Vision - ECCV 2020, 2020
Spike-FlowNet: Event-Based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks.
Proceedings of the Computer Vision - ECCV 2020, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives.
IEEE Trans. Computers, 2019
Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity.
IEEE Trans. Cogn. Dev. Syst., 2019
Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization.
CoRR, 2019
X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks.
CoRR, 2019
Synthesizing Images from Spatio-Temporal Representations using Spike-based Backpropagation.
CoRR, 2019
Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures.
CoRR, 2019
ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing.
CoRR, 2019
Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting.
CoRR, 2019
Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge.
CoRR, 2019
Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks.
IEEE Access, 2019
Proceedings of the IEEE International Conference on Smart Computing, 2019
Proceedings of the 16th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis.
Proceedings of the International Joint Conference on Neural Networks, 2019
On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the 2019 IEEE International Conference on Cognitive Computing, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data.
IEEE Trans. Multi Scale Comput. Syst., 2018
Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018
An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain.
IEEE Trans. Emerg. Top. Comput. Intell., 2018
Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars.
IEEE Trans. Emerg. Top. Comput. Intell., 2018
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.
CoRR, 2018
Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness.
CoRR, 2018
Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
CoRR, 2018
Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons.
CoRR, 2018
CoRR, 2018
Proposal for a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets.
CoRR, 2018
Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency.
CoRR, 2018
CoRR, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors.
Microelectron. Reliab., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
CoRR, 2017
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
CoRR, 2017
An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain.
CoRR, 2017
Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars.
CoRR, 2017
SPARE: Spiking Networks Acceleration Using CMOS ROM-Embedded RAM as an In-Memory-Computation Primitive.
CoRR, 2017
Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing.
CoRR, 2017
Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime.
CoRR, 2017
Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks.
CoRR, 2017
CoRR, 2017
Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion.
CoRR, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Spin-torque sensors with differential signaling for fast and energy efficient global interconnects.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper).
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Convolving over time via recurrent connections for sequential weight sharing in neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Fast, low power evaluation of elementary functions using radial basis function networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing.
IEEE Trans. Neural Networks Learn. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets.
IEEE Trans. Biomed. Circuits Syst., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes.
ACM J. Emerg. Technol. Comput. Syst., 2016
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
IEEE Des. Test, 2016
Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction.
CoRR, 2016
CoRR, 2016
Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition.
CoRR, 2016
Proposal for a Leaky-Integrate-Fire Spiking Neuron based on Magneto-Electric Switching of Ferro-magnets.
CoRR, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Spintronic devices for ultra-low power neuromorphic computation (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Unsupervised incremental STDP learning using forced firing of dormant or idle neurons.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Design of power-efficient approximate multipliers for approximate artificial neural networks.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Microelectron. Reliab., 2015
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.
ACM J. Emerg. Technol. Comput. Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
CoRR, 2015
Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets.
CoRR, 2015
Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses.
CoRR, 2015
Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems.
CoRR, 2015
CoRR, 2015
Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons.
CoRR, 2015
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. J., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR, 2014
CoRR, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
IEEE Des. Test, 2013
Spintronic Switches for Ultra Low Energy On-Chip and Inter-Chip Current-Mode Interconnects
CoRR, 2013
CoRR, 2013
CoRR, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes.
Proceedings of the Design, Automation and Test in Europe, 2013
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits.
Proceedings of the Design, Automation and Test in Europe, 2013
Ultra low power associative computing with spin neurons and resistive crossbar memory.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Analysis and characterization of inherent application resilience for approximate computing.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.
ACM J. Emerg. Technol. Comput. Syst., 2012
J. Circuits Syst. Comput., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Spin based neuron-synapse module for ultra low power programmable computational networks.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Energy efficient many-core processor for recognition and mining using spin-based memory.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2010
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2010
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2010
ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.
Proc. IEEE, 2010
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.
Proc. IEEE, 2010
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.
IEEE J. Solid State Circuits, 2010
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009
IEEE Des. Test Comput., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
Proceedings of the 46th Design Automation Conference, 2009
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.
J. Signal Process. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers, 2008
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008
J. Electron. Test., 2008
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
O<sup>2</sup>C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Device-Aware Yield-Centric Dual-V<sub>t</sub> Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Signal Process., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing.
J. Low Power Electron., 2007
IEICE Trans. Electron., 2007
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ.
Proceedings of the 2007 IEEE International Test Conference, 2007
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions.
Proceedings of the 2007 IEEE International Test Conference, 2007
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
A process variation aware low power synthesis methodology for fixed-point FIR filters.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion.
Proceedings of the IEEE International Conference on Acoustics, 2007
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.
Proceedings of the 44th Design Automation Conference, 2007
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
Proceedings of the 44th Design Automation Conference, 2007
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2006
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst., 2006
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE J. Solid State Circuits, 2006
J. Electron. Test., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Process Variation: Its Impact on the Design and Test of CMOS Circuits.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A novel wavelet transform-based transient current analysis for fault detection and localization.
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst., 2005
CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Computers, 2005
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid State Circuits, 2005
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test., 2005
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test., 2005
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Cascaded carry-select adder (C<sup>2</sup>SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Effectiveness of low power dual-V<sub>t</sub> designs in nano-scale technologies under process parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel low-complexity method for parallel multiplierless implementation of digital FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
Proceedings of the 2005 Design, 2005
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
Proceedings of the 2005 Design, 2005
A novel synthesis approach for active leakage power reduction using dynamic supply gating.
Proceedings of the 42nd Design Automation Conference, 2005
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Complexity reduction of digital filters using shift inclusive differential coefficients.
IEEE Trans. Signal Process., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Computation sharing programmable FIR filter for low-power and high-performance applications.
IEEE J. Solid State Circuits, 2004
IEEE Des. Test Comput., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Low-power carry-select adder using adaptive supply voltage based on input vector patterns.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Data-retention flip-flops for power-down applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Dual-edge triggered level converting flip-flops.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
A low power reconfigurable DCT architecture to trade off image quality for computational complexity.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Novel sizing algorithm for yield improvement under process variation in nanometer technology.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Process variation in nano-scale memories: failure analysis and process tolerant architecture.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array.
Proceedings of the International Conference on Communications in Computing, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Two's complement computation sharing multiplier and its applications to high performance DFE.
IEEE Trans. Signal Process., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Optimal body bias selection for leakage improvement and process compensation over different technology generations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A forward body-biased low-leakage SRAM cache: device and architecture considerations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies.
Proceedings of the ESSCIRC 2003, 2003
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
Proceedings of the 2003 Design, 2003
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
O<sup>2</sup>ABA: a novel high-performance predictable circuit architecture for the deep submicron era.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Des. Test Comput., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
A novel wavelet transform based transient current analysis for fault detection and localization.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.
VLSI Design, 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
On effective I<sub>DDQ</sub> testing of low-voltage CMOS circuits using leakage control techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001
A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis.
IEEE Trans. Signal Process., 2001
IEEE Des. Test Comput., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Reducing set-associative cache energy via way-prediction and selective direct-mapping.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Design and Test of Low Voltage CMOS Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Decision feedback equalizer with two's complement computation sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Des. Test Comput., 2000
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Gated-V<sub>dd</sub>: a circuit technique to reduce leakage in deep-submicron cache memories
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
A novel high-performance predictable circuit architecture for the deep sub-micron era.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Symposium on System Synthesis, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
High-level modeling of switching activity with application to low-power DSP system synthesis.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Mixed-<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Maximum power estimation for CMOS circuits using deterministic and statistical approaches.
IEEE Trans. Very Large Scale Integr. Syst., 1998
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Estimation of power sensitivity in sequential circuits with power macromodeling application.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Estimation of average switching power under accurate modeling of signal correlations.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
ACM Trans. Design Autom. Electr. Syst., 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Network-based simulation laboratories for microelectronics systems design and education.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
ACM Trans. Design Autom. Electr. Syst., 1996
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE J. Solid State Circuits, 1996
Maximum power estimation for CMOS circuits using deterministic and statistic approaches.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Estimation of sequential circuit activity considering spatial and temporal correlations.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Guest Editors' Introduction: Low-Power VLSI Design.
IEEE Des. Test Comput., 1994
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Estimation of circuit activity considering signal correlations and simultaneous switching.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the Field-Programmable Logic, 1994
Proceedings of the Field-Programmable Logic, 1994
Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects.
Proceedings of the Proceedings EURO-DAC'94, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1990
IEEE Trans. Computers, 1990
Proceedings of the European Design Automation Conference, 1990
1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988