Kaushik Roy

According to our database1, Kaushik Roy authored at least 733 papers between 1988 and 2020.

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Bibliography

2020
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays.
IEEE Trans. Circuits Syst., 2020

In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Logic Synthesis of Approximate Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.
IEEE Trans. Computers, 2020

Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.
Proc. IEEE, 2020

Tree-CNN: A hierarchical Deep Convolutional Neural Network for incremental learning.
Neural Networks, 2020

Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators.
IEEE Micro, 2020

CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

DCT-SNN: Using DCT to Distribute Spatial Information over Time for Learning Low-Latency Spiking Neural Networks.
CoRR, 2020

Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks?
CoRR, 2020

DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks.
CoRR, 2020

TREND: Transferability based Robust ENsemble Design.
CoRR, 2020

Towards Understanding the Effect of Leak in Spiking Neural Networks.
CoRR, 2020

Conditionally Deep Hybrid Neural Networks Across Edge and Cloud.
CoRR, 2020

IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Array.
CoRR, 2020

RMP-SNNs: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Networks.
CoRR, 2020

Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation.
CoRR, 2020

Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors.
CoRR, 2020

Structured Compression and Sharing of Representational Space for Continual Learning.
CoRR, 2020

Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing.
IEEE Access, 2020

A Low Effort Approach to Structured CNN Design Using PCA.
IEEE Access, 2020

Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.
IEEE Access, 2020

Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Energy-Efficient Target Recognition using ReRAM Crossbars for Enabling On-Device Intelligence.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation.
Proceedings of the 8th International Conference on Learning Representations, 2020

Training Deep Spiking Neural Networks for Energy-Efficient Neuromorphic Computing.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-linear Activations.
Proceedings of the Computer Vision - ECCV 2020, 2020

Spike-FlowNet: Event-Based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks.
Proceedings of the Computer Vision - ECCV 2020, 2020

GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Powerline Communication for Enhanced Connectivity in Neuromorphic Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives.
IEEE Trans. Computers, 2019

Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity.
IEEE Trans. Cogn. Dev. Syst., 2019

Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev., 2019

Structured Learning for Action Recognition in Videos.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization.
CoRR, 2019

X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks.
CoRR, 2019

Synthesizing Images from Spatio-Temporal Representations using Spike-based Backpropagation.
CoRR, 2019

Reinforcement Learning with Low-Complexity Liquid State Machines.
CoRR, 2019

PCA-driven Hybrid network design for enabling Intelligence at the Edge.
CoRR, 2019

Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures.
CoRR, 2019

ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing.
CoRR, 2019

Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting.
CoRR, 2019

Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge.
CoRR, 2019

Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks.
IEEE Access, 2019

Neural Networks at the Edge.
Proceedings of the IEEE International Conference on Smart Computing, 2019

A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2019

Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis.
Proceedings of the International Joint Conference on Neural Networks, 2019

On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2019

Scaling Deep Spiking Neural Networks with Binary Stochastic Activations.
Proceedings of the 2019 IEEE International Conference on Cognitive Computing, 2019

PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design.
Proceedings of the International Conference on Computer-Aided Design, 2019

Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Bayesian-based Hyperparameter Optimization for Spiking Neuromorphic Systems.
Proceedings of the 2019 IEEE International Conference on Big Data (Big Data), 2019

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Automatic Synthesis Techniques for Approximate Circuits.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
High-Density SOT-MRAM Based on Shared Bitline Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Computing in Memory With Spin-Transfer Torque Magnetic RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data.
IEEE Trans. Multi Scale Comput. Syst., 2018

Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain.
IEEE Trans. Emerg. Top. Comput. Intell., 2018

Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars.
IEEE Trans. Emerg. Top. Comput. Intell., 2018

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Image Edge Detection Based on Swarm Intelligence Using Memristive Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Adaptive accelerated aging for 28 nm HKMG technology.
Microelectron. Reliab., 2018

STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2018

Energy-Efficient Neural Computing with Approximate Multipliers.
ACM J. Emerg. Technol. Comput. Syst., 2018

Energy Efficient Neural Computing: A Study of Cross-Layer Approximations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.
CoRR, 2018

Photonic Spiking Neural Networks - From Devices to Systems.
CoRR, 2018

Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness.
CoRR, 2018

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays.
CoRR, 2018

Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons.
CoRR, 2018

All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light.
CoRR, 2018

Proposal for a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets.
CoRR, 2018

Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency.
CoRR, 2018

8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing.
CoRR, 2018

Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning.
CoRR, 2018

Going Deeper in Spiking Neural Networks: VGG and Residual Architectures.
CoRR, 2018

Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

M<sup>2</sup>CA: Modular Memristive Crossbar Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Accelerated BTI degradation under stochastic TDDB effect.
Proceedings of the IEEE International Reliability Physics Symposium, 2018


Computing-in-memory with spintronics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Object Detection Using Semantic Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2017

FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors.
Microelectron. Reliab., 2017

Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study.
ACM J. Emerg. Technol. Comput. Syst., 2017

Energy-Efficient and Improved Image Recognition with Conditional Deep Learning.
ACM J. Emerg. Technol. Comput. Syst., 2017

Chaos-guided Input Structuring for Improved Learning in Recurrent Neural Networks.
CoRR, 2017

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
CoRR, 2017

An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain.
CoRR, 2017

Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars.
CoRR, 2017

SPARE: Spiking Networks Acceleration Using CMOS ROM-Embedded RAM as an In-Memory-Computation Primitive.
CoRR, 2017

Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing.
CoRR, 2017

Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime.
CoRR, 2017

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference.
CoRR, 2017

Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks.
CoRR, 2017

Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets.
CoRR, 2017

Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion.
CoRR, 2017

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Gabor filter assisted energy efficient fast learning Convolutional Neural Networks.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper).
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Image segmentation with stochastic magnetic tunnel junctions and spiking neurons.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Convolving over time via recurrent connections for sequential weight sharing in neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Fast, low power evaluation of elementary functions using radial basis function networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Magnetic tunnel junction enabled all-spin stochastic spiking neural network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

STAxCache: An approximate, energy efficient STT-MRAM cache.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Semantic driven hierarchical learning for energy-efficient image classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing.
IEEE Trans. Neural Networks Learn. Syst., 2016

A Vision for All-Spin Neural Networks: A Device to System Perspective.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Cache Design with Domain Wall Memory.
IEEE Trans. Computers, 2016

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets.
IEEE Trans. Biomed. Circuits Syst., 2016

Spin-Transfer Torque Memories: Devices, Circuits, and Systems.
Proc. IEEE, 2016

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC.
ACM J. Emerg. Technol. Comput. Syst., 2016

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes.
ACM J. Emerg. Technol. Comput. Syst., 2016

High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
IEEE Des. Test, 2016

Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction.
CoRR, 2016

Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction.
CoRR, 2016

Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition.
CoRR, 2016

Proposal for a Leaky-Integrate-Fire Spiking Neuron based on Magneto-Electric Switching of Ferro-magnets.
CoRR, 2016

MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic.
CoRR, 2016

Approximate Computing.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Neuromorphic Computing Enabled by Spin-Transfer Torque Devices.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Spin transfer torque memories for on-chip caches: Prospects and perspectives.
Proceedings of the 17th Latin-American Test Symposium, 2016

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Spintronic devices for ultra-low power neuromorphic computation (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Spin torque nano-oscillator based Oscillatory Neural Network.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

On the energy benefits of spiking deep neural networks: A case study.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Unsupervised incremental STDP learning using forced firing of dormant or idle neurons.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Design of power-efficient approximate multipliers for approximate artificial neural networks.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Conditional Deep Learning for energy-efficient and enhanced pattern recognition.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Designing approximate circuits using clock overgating.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Toward a spintronic deep learning spiking neural processor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Computing with coupled Spin Torque Nano Oscillators.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Efficient embedded learning for IoT devices.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Exploring Spin-Transfer-Torque Devices for Logic Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Ultra-thin dielectric breakdown in devices and circuits: A brief review.
Microelectron. Reliab., 2015

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.
ACM J. Emerg. Technol. Comput. Syst., 2015

Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Guest Editorial Computing in Emerging Technologies (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

High Sensitivity Biosensor using Injection Locked Spin Torque Nano-Oscillators.
CoRR, 2015

Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets.
CoRR, 2015

Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses.
CoRR, 2015

Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons.
CoRR, 2015

Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems.
CoRR, 2015

Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing.
CoRR, 2015

Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons.
CoRR, 2015

Spin-Torque Sensors for Energy Efficient High Speed Long Interconnects.
CoRR, 2015

Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Computing approximately, and efficiently.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Device/circuit/architecture co-design of reliable STT-MRAM.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Asymmetric underlapped FinFET based robust SRAM design at 7nm node.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate computing and the quest for computing efficiency.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Approximate storage for energy efficient spintronic memories.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Scalable Effort Hardware Design.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology.
Microelectron. J., 2014

Guest Editorial Computing in Emerging Technologies (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Spin Orbit Torque Based Electronic Neuron.
CoRR, 2014

Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity.
CoRR, 2014

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR, 2014

Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic.
CoRR, 2014

Laser Induced Magnetization Reversal for Detection in Optical Interconnects.
CoRR, 2014

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

AxNN: energy-efficient neuromorphic systems using approximate computing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

StoRM: a stochastic recognition and mining processor.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Approximate computing for efficient information processing.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Brain-inspired computing with spin torque devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ASLAN: Synthesis of approximate sequential circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

"All Programmable SOC FPGA for networking and computing in big data infrastructure".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Area Efficient ROM-Embedded SRAM Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling.
ACM Trans. Embed. Comput. Syst., 2013

Low-Power Digital Signal Processing Using Approximate Adders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.
IEEE Trans. Computers, 2013

Dual pillar spin-transfer torque MRAMs for low power applications.
ACM J. Emerg. Technol. Comput. Syst., 2013

Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs.
IEEE Des. Test, 2013

Spintronic Switches for Ultra Low Energy On-Chip and Inter-Chip Current-Mode Interconnects
CoRR, 2013

Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers.
CoRR, 2013

Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic.
CoRR, 2013

Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic.
CoRR, 2013

Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices.
CoRR, 2013

Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Reading spin-torque memory with spin-torque sensors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Quality programmable vector processors for approximate computing.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Design of ultra high density and low power computational blocks using nano-magnets.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Low power and compact mixed-mode signal processing hardware using spin-neurons.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Approximate computing: Energy-efficient computing with good-enough results.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Exploring Boolean and non-Boolean computing with spin torque devices.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Approximate computing for energy-efficient error-resilient multimedia systems.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes.
Proceedings of the Design, Automation and Test in Europe, 2013

Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Ultra low power associative computing with spin neurons and resistive crossbar memory.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Analysis and characterization of inherent application resilience for approximate computing.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy-efficient recognition and mining processor using scalable effort design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Approximate computing: An integrated hardware approach.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst., 2012

Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst., 2012

CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Viterbi-Based Efficient Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.
ACM J. Emerg. Technol. Comput. Syst., 2012

Self-Healing Design in Deep Scaled CMOS Technologies.
J. Circuits Syst. Comput., 2012

Verifying Reliability (Dagstuhl Seminar 12341).
Dagstuhl Reports, 2012

Proposal For Neuromorphic Hardware Using Spin Devices
CoRR, 2012

HBIST: An approach towards zero external test cost.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012

Ultra low energy analog image processing using spin based neurons.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Variation-aware and self-healing design methodology for a system-on-chip.
Proceedings of the 13th Latin American Test Workshop, 2012

TapeCache: a high density, energy efficient cache based on domain wall memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

High-performance low-energy STT MRAM based on balanced write scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Write-optimized reliable design of STT MRAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Spin based neuron-synapse module for ultra low power programmable computational networks.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Functional analysis of circuits under timing variations.
Proceedings of the 17th IEEE European Test Symposium, 2012

On Modeling and Evaluation of Logic Circuits under Timing Variations.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Layout-aware optimization of stt mrams.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SALSA: systematic logic synthesis of approximate circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Cognitive computing with spin-based neural networks.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Efficient Design of Micro-Scale Energy Harvesting Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Memory-based embedded digital ATE.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Energy efficient many-core processor for recognition and mining using spin-based memory.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Low-power functionality enhanced computation architecture using spin-based devices.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Scaled LTPS TFTs for low-cost low-power applications.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

IMPACT: imprecise adders for low-power approximate computing.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

MACACO: Modeling and analysis of circuits for approximate computing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Voltage over-scaling: A cross-layer design perspective for energy efficient systems.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Design of voltage-scalable meta-functions for approximate computing.
Proceedings of the Design, Automation and Test in Europe, 2011

Stage number optimization for switched capacitor power converters in micro-scale energy harvesting.
Proceedings of the Design, Automation and Test in Europe, 2011

Significance driven computation on next-generation unreliable platforms.
Proceedings of the 48th Design Automation Conference, 2011

Dynamic effort scaling: managing the quality-efficiency tradeoff.
Proceedings of the 48th Design Automation Conference, 2011

Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Low-Power and Variation-Tolerant Application-Specific System Design.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Self-Repairing SRAM Using On-Chip Detection and Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2010

ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.
Proc. IEEE, 2010

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.
Proc. IEEE, 2010

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.
IEEE J. Solid State Circuits, 2010

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010

Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Analysis and design of ultra low power thermoelectric energy harvesting systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Maximum power point considerations in micro-scale solar energy harvesting systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.
Proceedings of the 28th International Conference on Computer Design, 2010

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.
Proceedings of the 15th European Test Symposium, 2010

Efficient power conversion for ultra low voltage micro scale energy transducers.
Proceedings of the Design, Automation and Test in Europe, 2010

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
Proceedings of the 47th Design Automation Conference, 2010

Data-dependant sense-amplifier flip-flop for low power applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Micro-scale energy harvesting: a system design perspective.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Improved clock-gating control scheme for transparent pipeline.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009

Reliability Implications of Bias-Temperature Instability in Digital ICs.
IEEE Des. Test Comput., 2009

Coping with Variations through System-Level Design.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design in the nano-scale Era: Low-power, reliability, and error resiliency.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Impact of SoC power management techniques on verification and testing.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Ultra low voltage CMOS.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Device/circuit interactions at 22nm technology node.
Proceedings of the 46th Design Automation Conference, 2009

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
Proceedings of the 46th Design Automation Conference, 2009

REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.
J. Signal Process. Syst., 2008

Profit Aware Circuit Design Under Process Variations Considering Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers, 2008

An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008

A Low-Power SRAM Using Bit-Line Charge-Recycling.
IEEE J. Solid State Circuits, 2008

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.
J. Electron. Test., 2008

Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Tutorial: SoC Power Management Verification and Testing Issues.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Thermal analysis of 8-T SRAM for nano-scaled technologies.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

O<sup>2</sup>C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Low power design under parameter variations.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Panel: SoC power management implications on validation and testing.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Soft Errors: System Effects, Protection Techniques and Case Studies.
Proceedings of the Design, Automation and Test in Europe, 2008

Power-Aware Testing and Test Strategies for Low Power Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.
Proceedings of the Design, Automation and Test in Europe, 2008

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
Proceedings of the 45th Design Automation Conference, 2008

Process variation tolerant SRAM array for ultra low voltage applications.
Proceedings of the 45th Design Automation Conference, 2008

A high sensitivity process variation sensor utilizing sub-threshold operation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Device-Aware Yield-Centric Dual-V<sub>t</sub> Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Design of Sigma-Delta Modulators With Arbitrary Transfer Functions.
IEEE Trans. Signal Process., 2007

Low-Power and testable circuit synthesis using Shannon decomposition.
ACM Trans. Design Autom. Electr. Syst., 2007

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Guest Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS.
IEEE J. Solid State Circuits, 2007

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM.
IEEE J. Solid State Circuits, 2007

Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing.
J. Low Power Electron., 2007

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders.
IEICE Trans. Electron., 2007

An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Process Variations and Process-Tolerant Design.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.
Proceedings of the 2007 IEEE International Test Conference, 2007

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ.
Proceedings of the 2007 IEEE International Test Conference, 2007

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions.
Proceedings of the 2007 IEEE International Test Conference, 2007

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Fine-Grained Redundancy in Adders.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A High Performance, Scalable Multiplexed Keeper Technique.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

FinFET Based SRAM Design for Low Standby Power Applications.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A low-power SRAM using bit-line charge-recycling technique.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A process variation aware low power synthesis methodology for fixed-point FIR filters.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Tolerance to Small Delay Defects by Adaptive Clock Stretching.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

The effect of process variation on device temperature in FinFET circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion.
Proceedings of the IEEE International Conference on Acoustics, 2007

Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Process variation tolerant low power DCT architecture.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

High Performance and Low Power Electronics on Flexible Substrate.
Proceedings of the 44th Design Automation Conference, 2007

Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.
Proceedings of the 44th Design Automation Conference, 2007

Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
Proceedings of the 44th Design Automation Conference, 2007

FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Layout-driven architecture synthesis for high-speed digital filters.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst., 2006

Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient modeling of 1/f<sup>alpha</sup>/ noise using multirate process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modeling and Analysis of Leakage Currents in Double-Gate Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro, 2006

Guest Editorial.
Integr., 2006

Low-power design techniques for scaled technologies.
Integr., 2006

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
J. Electron. Test., 2006

Test Consideration for Nanometer-Scale CMOS Circuits.
IEEE Des. Test Comput., 2006

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Minimizing Ohmic Loss in Future Processor IR Events.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analysis of super cut-off transistors for ultralow power digital logic circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Robust level converter design for sub-threshold logic.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low power synthesis of dynamic logic circuits using fine-grained clock gating.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006

A high density, carbon nanotube capacitor for decoupling applications.
Proceedings of the 43rd Design Automation Conference, 2006

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.
Proceedings of the 43rd Design Automation Conference, 2006

Integrated MEMS Switches for Leakage Control of Battery Operated Systems.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Speed binning aware design methodology to improve profit under parameter variations.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A novel wavelet transform-based transient current analysis for fault detection and localization.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Low-power scan design using first-level supply gating.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A process-tolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst., 2005

Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embed. Comput. Syst., 2005

CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
IEEE Trans. Computers, 2005

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test., 2005

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test., 2005

Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A leakage control system for thermal stability during burn-in test.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Cascaded carry-select adder (C<sup>2</sup>SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Effectiveness of low power dual-V<sub>t</sub> designs in nano-scale technologies under process parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel low-complexity method for parallel multiplierless implementation of digital FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Process Variation Tolerant Online Current Monitor for Robust Systems.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Feasibility Study of Subthreshold SRAM Across Technology Generations.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A Soft Error Monitor Using Switching Current Detection.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Double-gate SOI devices for low-power and high-performance applications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Joint control of communication subsystems for low-energy image transmission.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Energy recovery clocked dynamic logic.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
Proceedings of the 2005 Design, 2005

Statistical Timing Analysis using Levelized Covariance Propagation.
Proceedings of the 2005 Design, 2005

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
Proceedings of the 2005 Design, 2005

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
Proceedings of the 2005 Design, 2005

A novel synthesis approach for active leakage power reduction using dynamic supply gating.
Proceedings of the 42nd Design Automation Conference, 2005

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Complexity reduction of digital filters using shift inclusive differential coefficients.
IEEE Trans. Signal Process., 2004

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A circuit-compatible model of ballistic carbon nanotube field-effect transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses.
IEEE Des. Test Comput., 2004

Enhancing Yield at the End of the Technology Roadmap.
IEEE Des. Test Comput., 2004

Modeling and Estimation of Leakage in Sub-90nm Devices.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A leakage-tolerant low-leakage register file with conditional sleep transistor.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Low-Power Design.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

FinFET SRAM - Device and Circuit Design Considerations.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Low-power carry-select adder using adaptive supply voltage based on input vector patterns.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Device optimization for ultra-low power digital sub-threshold operation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Data-retention flip-flops for power-down applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Dual-edge triggered level converting flip-flops.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Technique to Reduce Power and Test Application Time in BIST.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A Novel Low-Power Scan Design Technique Using Supply Gating.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Statistical design and optimization of SRAM cell for yield enhancement.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A low power reconfigurable DCT architecture to trade off image quality for computational complexity.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
Proceedings of the 2004 Design, 2004

Novel sizing algorithm for yield improvement under process variation in nanometer technology.
Proceedings of the 41th Design Automation Conference, 2004

Leakage in nano-scale technologies: mechanisms, impact and design considerations.
Proceedings of the 41th Design Automation Conference, 2004

Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Process variation in nano-scale memories: failure analysis and process tolerant architecture.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array.
Proceedings of the International Conference on Communications in Computing, 2004

Adaptive supply voltage technique for low swing interconnects.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
High-performance FIR filter design based on sharing multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Gate leakage reduction for scaled devices using transistor stacking.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Ultra-low-power DLMS adaptive filter for hearing aid applications.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Multiple-parameter CMOS IC testing with increased sensitivity for I<sub>DDQ</sub>.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Two's complement computation sharing multiplier and its applications to high performance DFE.
IEEE Trans. Signal Process., 2003

On-chip interconnect modeling by wire duplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Design of Deep Sub-Micron CMOS Circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Optimal body bias selection for leakage improvement and process compensation over different technology generations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A forward body-biased low-leakage SRAM cache: device and architecture considerations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Energy recovery clocking scheme and flip-flops for ultra low-energy applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A logic-aware layout methodology to enhance the noise immunity of domino circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low Power Adder with Adaptive Supply Voltage.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Deterministic Clock Gating for Microprocessor Power Reduction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
Proceedings of the 2003 Design, 2003

MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.
Proceedings of the 2003 Design, 2003

A New Crosstalk Noise Model for DOMINO Logic Circuits.
Proceedings of the 2003 Design, 2003

Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
Proceedings of the 2003 Design, 2003

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology.
Proceedings of the 2003 Design, 2003

An adaptive window-based susceptance extraction and its efficient implementation.
Proceedings of the 40th Design Automation Conference, 2003

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
Proceedings of the 40th Design Automation Conference, 2003

A metric for analyzing effective on-chip inductive coupling.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Robust high-performance low-power carry select adder.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Integer linear programming-based synthesis of skewed logic circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology.
Proceedings of the Embedded Software for SoC, 2003

2002
Vertically integrated SOI circuits for low-power and high-performance applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2002

O<sup>2</sup>ABA: a novel high-performance predictable circuit architecture for the deep submicron era.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Leakage Current in Deep-Submicron CMOS Circuits.
J. Circuits Syst. Comput., 2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Des. Test Comput., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Des. Test Comput., 2002

Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Dynamic Noise Analysis with Capacitive and Inductive Coupling.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Synthesis of Selectively Clocked Skewed Logic Circuits.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

High performance and low power FIR filter design based on sharing multiplication.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Low power reconfigurable DCT design based on sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2002

Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Dynamic VTH Scaling Scheme for Active Leakage Power Reduction.
Proceedings of the 2002 Design, 2002

Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.
Proceedings of the 2002 Design, 2002

Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis.
Proceedings of the 2002 Design, 2002

Timed pattern generation for noise-on-delay calculation.
Proceedings of the 39th Design Automation Conference, 2002

A novel wavelet transform based transient current analysis for fault detection and localization.
Proceedings of the 39th Design Automation Conference, 2002

DRG-cache: a data retention gated-ground cache for low power.
Proceedings of the 39th Design Automation Conference, 2002

A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.
VLSI Design, 2001

Robust subthreshold logic for ultra-low power operation.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Reducing leakage in a high-performance deep-submicron instruction cache.
IEEE Trans. Very Large Scale Integr. Syst., 2001

On effective I<sub>DDQ</sub> testing of low-voltage CMOS circuits using leakage control techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001

A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis.
IEEE Trans. Signal Process., 2001

Fault Detection and Location Using IDD Waveform Analysis.
IEEE Des. Test Comput., 2001

Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Reducing set-associative cache energy via way-prediction and selective direct-mapping.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Design and Test of Low Voltage CMOS Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Decoupling capacitance allocation for power supply noise suppression.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Ultra-low power DLMS adaptive filter for hearing aid applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Power trends and performance characterization of 3-dimensional integration.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Short-circuit power analysis of an inverter driving an RLC load.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power Constrained Test Scheduling with Low Power Weighted Random Testing.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Decision feedback equalizer with two's complement computation sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2001

DSP data path synthesis for low-power applications.
Proceedings of the IEEE International Conference on Acoustics, 2001

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Low complexity FIR filters using factorization of perturbed coefficients.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration.
Proceedings of the 38th Design Automation Conference, 2001

Design Verification and Robust Design Technique for Cross-Talk Faults.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Low-power weighted random pattern testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Estimation of power dissipation using a novel power macromodelingtechnique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Estimating Circuit Activity in Combinational CMOS Digital Circuits.
IEEE Des. Test Comput., 2000

Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Low Power VLSI Signal Processing.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Peak Power Reduction in Low Power BIST.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Robust ultra-low power sub-threshold DTMOS logic.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Power Reduction in Test-Per-Scan BIST.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Frequency Domain Analysis of Switching Noise on Power Supply Network.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Non-adaptive and adaptive filter implementation based on sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2000

Minimally redundant parallel implementation of digital filters and vector scaling.
Proceedings of the IEEE International Conference on Acoustics, 2000

Digital CMOS logic operation in the sub-threshold region.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Dynamic noise analysis in precharge-evaluate circuits.
Proceedings of the 37th Conference on Design Automation, 2000

Test challenges for deep sub-micron technologies.
Proceedings of the 37th Conference on Design Automation, 2000

Low-Power CMOS VLSI Circuit Design.
Wiley, ISBN: 978-0-471-11488-8, 2000

1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Low Power Design Methodologies for Systems-on-Chips.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

VLSI Signal Processing in FPGAs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Ultra-low power digital subthreshold logic circuits.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.
Proceedings of the IEEE International Conference On Computer Design, 1999

A novel design methodology for high performance and low power digital filters.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

High-level modeling of switching activity with application to low-power DSP system synthesis.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Mixed-<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS.
Proceedings of the 36th Conference on Design Automation, 1999

Power Consumption in XOR-Based Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Performance and Wirability Driven Layout for Row-Based FPGAs.
VLSI Design, 1998

Maximum power estimation for CMOS circuits using deterministic and statistical approaches.
IEEE Trans. Very Large Scale Integr. Syst., 1998

LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Power Estimation Under Uncertain Delays.
Integr. Comput. Aided Eng., 1998

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Estimation of power sensitivity in sequential circuits with power macromodeling application.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998

A Power Macromodeling Technique Based on Power Sensitivity.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Datapath scheduling with multiple supply voltages and level converters.
ACM Trans. Design Autom. Electr. Syst., 1997

Algorithms for Low Power FIR Filter Realization Using Differential Coefficients.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Network-based simulation laboratories for microelectronics systems design and education.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Quasi-static energy recovery logic and supply-clock generation circuits.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

LVDCSL: low voltage differential current switch logic, a robust low power DCSL family.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A Graph-Based Synthesis Algorithm for AND/XOR Networks.
Proceedings of the 34st Conference on Design Automation, 1997

Efficient synthesis of AND/XOR networks.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Accurate power estimation of CMOS sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Transistor reordering for power minimization under delay constraint.
ACM Trans. Design Autom. Electr. Syst., 1996

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Maximum power estimation for CMOS circuits using deterministic and statistic approaches.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
On Routability for FPGAs under Faulty Conditions.
IEEE Trans. Computers, 1995

Circuit optimization for minimisation of power consumption under delay constraint.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Integrated Test Solutions and Test Economics for MCMs.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Control unit synthesis targeting low-power processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Estimation of sequential circuit activity considering spatial and temporal correlations.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Statistical estimation of sequential circuit activity.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Automatic synthesis of FPGA channel architecture for routability and performance.
IEEE Trans. Very Large Scale Integr. Syst., 1994

BiCMOS logic testing.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Guest Editors' Introduction: Low-Power VLSI Design.
IEEE Des. Test Comput., 1994

ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Estimation of circuit activity considering signal correlations and simultaneous switching.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Power Dissipation Driven FPGA Place and Route Under Delay Constraints.
Proceedings of the Field-Programmable Logic, 1994

On Channel Architecture and Routability for FPGAs Under Faulty Conditions.
Proceedings of the Field-Programmable Logic, 1994

Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
Circuit activity based logic synthesis for low power reliable operations.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures.
Proceedings of the Sixth International Conference on VLSI Design, 1993

On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Iterative Wirability and Performance Improvement for FPGAs.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
SYCLOP: Synthesis of CMOS Logic for Low Power Applications.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1990
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor.
IEEE Trans. Computers, 1990

High level test generation using data flow descriptions.
Proceedings of the European Design Automation Conference, 1990

1989
Synthesis of delay fault testable combinational logic.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A Novel Approach to Accurate Timing Verification Using RTL Descriptions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988


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