On Thermal Effects in Deep Sub-Micron VLSI Interconnects. - Kaustav Banerjee; Amit Mehrotra; Alberto L. Sangiovanni-Vincentelli; Chenming Hu (DAC, 1999)

Multiple Si layer ICs: motivation, performance analysis, and design implications. - Shukri J. Souri; Kaustav Banerjee; Amit Mehrotra; Krishna Saraswat (DAC, 2000)

Performance analysis and technology of 3-D ICs. - Krishna Saraswat; Shukri J. Souri; Kaustav Banerjee; Pawan Kapur (SLIP, 2000)

Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs. - Amir H. Ajami; Massoud Pedram; Kaustav Banerjee (CICC, 2001)

A fast analytical technique for estimating the bounds of on-chip clock wire inductance. - Yi-Chang Lu; Kaustav Banerjee; Mustafa Celik; Robert W. Dutton (CICC, 2001)

Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. - Amir H. Ajami; Kaustav Banerjee; Massoud Pedram; Lukas P. P. P. van Ginneken (DAC, 2001)

Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. - Kaustav Banerjee; Amit Mehrotra (DAC, 2001)

Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. - Amir H. Ajami; Kaustav Banerjee; Massoud Pedram (ICCAD, 2001)

Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. - Kaustav Banerjee; Amit Mehrotra (ICCAD, 2001)

Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. - TingYen Chiang; Kaustav Banerjee; Krishna Saraswat (ICCAD, 2001)

Analysis and optimization of thermal issues in high-performance VLSI. - Kaustav Banerjee; Massoud Pedram; Amir H. Ajami (ISPD, 2001)

Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. - Choshu Ito; Kaustav Banerjee; Robert W. Dutton (ISQED, 2001)

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. - Kaustav Banerjee; Shukri J. Souri; Pawan Kapur; Krishna C. Saraswat (Proc. IEEE, 2001)

Interconnect limits on gigascale integration (GSI) in the 21st century. - Jeffery A. Davis; Raguraman Venkatesan; Alan Kaloyeros; Michael Beylansky; Shukri J. Souri; Kaustav Banerjee; Krishna C. Saraswat; Arifur Rahman; Rafael Reif; James D. Meindl (Proc. IEEE, 2001)

Few electron devices: towards hybrid CMOS-SET integrated circuits. - Adrian M. Ionescu; Michel J. Declercq; Santanu Mahapatra; Kaustav Banerjee; Jacques Gautier (DAC, 2002)

Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. - Adil Koukab; Kaustav Banerjee; Michel J. Declercq (ICCAD, 2002)

A SET quantizer circuit aiming at digital communication system. - Santanu Mahapatra; Adrian M. Ionescu; Kaustav Banerjee; Michel J. Declercq (ISCAS (5), 2002)

Inductance Aware Interconnect Scaling. - Kaustav Banerjee; Amit Mehrotra (ISQED, 2002)

Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. - Adrian M. Ionescu; V. Pott; R. Fritschi; Kaustav Banerjee; Michel J. Declercq; Philippe Renaud; C. Hibert; Philippe Flückiger; G. A. Racine (ISQED, 2002)

Analysis of on-chip inductance effects for distributed RLC interconnects. - Kaustav Banerjee; Amit Mehrotra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Nano, quantum, and molecular computing: are we ready for the validation and test challenges? - Sandeep K. Shukla; Ramesh Karri; Seth Copen Goldstein; Forrest Brewer; Kaustav Banerjee; Sankar Basu (HLDVT, 2003)

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. - Santanu Mahapatra; Kaustav Banerjee; Florent Pegeon; Adrian M. Ionescu (ICCAD, 2003)

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. - Anirban Basu; Sheng-Chih Lin; Vineet Wason; Amit Mehrotra; Kaustav Banerjee (DAC, 2004)

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. - Songqing Zhang; Vineet Wason; Kaustav Banerjee (ISLPED, 2004)

A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. - Anirban Basu; Sheng-Chih Lin; Christoph Wasshuber; Adrian M. Ionescu; Kaustav Banerjee (ISQED, 2004)

Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . - Man Lung Mui; Kaustav Banerjee; Amit Mehrotra (ISQED, 2004)

Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. - Adil Koukab; Kaustav Banerjee; Michel J. Declercq (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Performance analysis of carbon nanotube interconnects for VLSI applications. - Navin Srivastava; Kaustav Banerjee (ICCAD, 2005)

A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. - Sheng-Chih Lin; Navin Srivastava; Kaustav Banerjee (ICCD, 2005)

A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. - Vineet Wason; Kaustav Banerjee (ISLPED, 2005)

Plenary Session 2P. - Lech Józwiak; Kaustav Banerjee (ISQED, 2005)

Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. - Navin Srivastava; Xiaoning Qi; Kaustav Banerjee (ISQED, 2005)

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. - Amir H. Ajami; Kaustav Banerjee; Massoud Pedram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Supply and power optimization in leakage-dominant technologies. - Man Lung Mui; Kaustav Banerjee; Amit Mehrotra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. - Kaustav Banerjee; Sheng-Chih Lin; Navin Srivastava (ASP-DAC, 2006)

Introspective 3D chips. - Shashidhar Mysore; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Kaustav Banerjee; Timothy Sherwood (ASPLOS, 2006)

Are carbon nanotubes the future of VLSI interconnections? - Kaustav Banerjee; Navin Srivastava (DAC, 2006)

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. - Hamed F. Dadgour; Rajiv V. Joshi; Kaustav Banerjee (DAC, 2006)

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. - Gian Luca Loi; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Timothy Sherwood; Kaustav Banerjee (DAC, 2006)

An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. - Sheng-Chih Lin; Kaustav Banerjee (ICCAD, 2006)

Tutorial 1: Emerging Technologies for VLSI Design. - Rajiv V. Joshi; Kaustav Banerjee; André DeHon (ISQED, 2006)

Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? - Kaustav Banerjee; Sungjun Im; Navin Srivastava (Nano-Net, 2006)

Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. - Hamed F. Dadgour; Kaustav Banerjee (DAC, 2007)

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. - Nikil D. Dutt; Kaustav Banerjee; Luca Benini; Kanishka Lahiri; Sudeep Pasricha (VLSI Design, 2007)

3D Integration for Introspection. - Shashidhar Mysore; Banit Agrawal; Navin Srivastava; Sheng-Chih Lin; Kaustav Banerjee; Timothy Sherwood (IEEE Micro, 2007)

Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. - Chaitanya Kshirsagar; Mohamed N. El-Zeftawi; Kaustav Banerjee (DAC, 2008)

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2008)

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. - Hamed F. Dadgour; Vivek De; Kaustav Banerjee (ICCAD, 2008)

A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. - Sheng-Chih Lin; Kaustav Banerjee (IEEE Trans. Very Large Scale Integr. Syst., 2008)

High-speed low-power FinFET based domino logic. - Seid Hadi Rasouli; Hanpei Koike; Kaustav Banerjee (ASP-DAC, 2009)

CMOS vs Nano: comrades or rivals? - Deming Chen; Russell Tessier; Kaustav Banerjee; Mojy C. Chian; André DeHon; Shinobu Fujita; James Hutchby; Steve Trimberger (FPGA, 2009)

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. - Seid Hadi Rasouli; Kazuhiko Endo; Kaustav Banerjee (ICCAD, 2009)

Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. - Chuan Xu; Lijun Jiang; Seshadri K. Kolluri; Barry J. Rubin; Alina Deutsch; Howard H. Smith; Kaustav Banerjee (ICCAD, 2009)

Graphene based transistors: physics, status and future perspectives. - Kaustav Banerjee; Yasin Khatami; Chaitanya Kshirsagar; Seid Hadi Rasouli (ISPD, 2009)

Graphene based nanomaterials for VLSI interconnect and energy-storage applications. - Kaustav Banerjee (SLIP, 2009)

Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs. - Hamed F. Dadgour; Kaustav Banerjee (IET Comput. Digit. Tech., 2009)

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. - Hamed F. Dadgour; Muhammad Mustafa Hussain; Casey Smith; Kaustav Banerjee (DAC, 2010)

Aging-resilient design of pipelined architectures using novel detection and correction circuits. - Hamed F. Dadgour; Kaustav Banerjee (DATE, 2010)

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2010)

Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design. - Seid Hadi Rasouli; Kazuhiko Endo; Kaustav Banerjee (ICCAD, 2010)

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. - Hamed F. Dadgour; Muhammad Mustafa Hussain; Kaustav Banerjee (ISLPED, 2010)

Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs. - Hong Li; Chuan Xu; Kaustav Banerjee (IEEE Des. Test Comput., 2010)

Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. - Navin Srivastava; Chuan Xu; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates. - Hamed F. Dadgour; Kaustav Banerjee (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. - Chuan Xu; Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

2D electronics: Graphene and beyond. - Wei Cao; Jiahao Kang; Wei Liu 067; Yasin Khatami; Deblina Sarkar; Kaustav Banerjee (ESSDERC, 2013)

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability. - Chuan Xu; Seshadri K. Kolluri; Kazuhiko Endo; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability". - Chuan Xu; Seshadri K. Kolluri; Kazuhiko Endo; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Exploration and Exploitation of Strain Engineering in 2D-FETs. - Ankit Kumar; Arnab Pal; Kamyar Parto; Wei Cao; Kaustav Banerjee (DRC, 2023)