Low-Power Perceptron Branch Predictor. - Kaveh Aasaraai; Amirali Baniasadi (J. Low Power Electron., 2006)

A Power-Aware Alternative for the Perceptron Branch Predictor. - Kaveh Aasaraai; Amirali Baniasadi (Asia-Pacific Computer Systems Architecture Conference, 2007)

Computational and storage power optimizations for the O-GEHL branch predictor. - Kaveh Aasaraai; Amirali Baniasadi; Ehsan Atoofian (Conf. Computing Frontiers, 2007)

Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. - Ehsan Atoofian; Amirali Baniasadi; Kaveh Aasaraai (Conf. Computing Frontiers, 2007)

Exploiting Speculation Cost Prediction in Power-Aware Applications. - Ehsan Atoofian; Amirali Baniasadi; Kaveh Aasaraai (J. Low Power Electron., 2007)

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. - Kaveh Aasaraai; Andreas Moshovos (FPL, 2009)

Design space exploration of instruction schedulers for out-of-order soft processors. - Kaveh Aasaraai; Andreas Moshovos (FPT, 2010)

An Efficient Non-blocking Data Cache for Soft Processors. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2010)

Caliper: a tool to generate precise and closed-loop traffic. - Monia Ghobadi; Martin Labrecque; Geoffrey Salmon; Kaveh Aasaraai; Soheil Hassas Yeganeh; Yashar Ganjali; J. Gregory Steffan (SIGCOMM, 2010)

Toward virtualizing branch direction prediction. - Maryam Sadooghi-Alvandi; Kaveh Aasaraai; Andreas Moshovos (DATE, 2012)

SPREX: A soft processor with Runahead execution. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2012)

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution. - Kaveh Aasaraai; Andreas Moshovos (Int. J. Reconfigurable Comput., 2012)

Low-cost, high-performance branch predictors for soft processors. - Di Wu 006; Kaveh Aasaraai; Andreas Moshovos (FPL, 2013)

An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design. - Kaveh Aasaraai; Andreas Moshovos (FCCM, 2014)

What limits the operating frequency of a soft processor design. - Kaveh Aasaraai; Andreas Moshovos (ReConFig, 2014)

RAW 2018 Invited Talks. - Jürgen Becker 001; Viktor K. Prasanna; Markus Weimer; Wayne Luk; Kaveh Aasaraai; Derek Chiou (IPDPS Workshops, 2018)

FPGA Acceleration of Multi-Scalar Multiplication: CycloneMSM. - Kaveh Aasaraai; Don Beaver; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela (IACR Cryptol. ePrint Arch., 2022)

CycloneNTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. - Kaveh Aasaraai; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela; Kevin Bowers (IACR Cryptol. ePrint Arch., 2022)

Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. - Kaveh Aasaraai; Emanuele Cesena; Rahul Maganti; Nicolas Stalder; Javier Varela; Kevin Bowers (FPGA, 2023)