Implicit pseudo boolean enumeration algorithms for input vector control. - Kaviraj Chopra; Sarma B. K. Vrudhula (DAC, 2004)

A Framework for Battery-Aware Sensor Management. - Sridhar Dasika; Sarma B. K. Vrudhula; Kaviraj Chopra; R. Srinivasan (DATE, 2004)

Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. - Kaviraj Chopra; Sarma B. K. Vrudhula; Sarvesh Bhardwaj (VLSI Design, 2004)

Circuit optimization using statistical static timing analysis. - Aseem Agarwal; Kaviraj Chopra; David T. Blaauw; Vladimir Zolotov (DAC, 2005)

CAD tools for variation tolerance. - David T. Blaauw; Kaviraj Chopra (DAC, 2005)

Statistical Timing Based Optimization using Gate Sizing. - Aseem Agarwal; Kaviraj Chopra; David T. Blaauw (DATE, 2005)

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. - Kaviraj Chopra; Saumil Shah; Ashish Srivastava; David T. Blaauw; Dennis Sylvester (ICCAD, 2005)

An efficient static algorithm for computing the soft error rates of combinational circuits. - Rajeev R. Rao; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (DATE, 2006)

A new statistical max operation for propagating skewness in statistical timing analysis. - Kaviraj Chopra; Bo Zhai; David T. Blaauw; Dennis Sylvester (ICCAD, 2006)

Analysis and modeling of CD variation for statistical static timing. - Brian Cline; Kaviraj Chopra; David T. Blaauw; Yu Cao (ICCAD, 2006)

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. - Kaviraj Chopra; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Top-k Aggressors Sets in Delay Noise Analysis. - Ravikishore Gandikota; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester; Murat R. Becer (DAC, 2007)

Victim alignment in crosstalk aware timing analysis. - Ravikishore Gandikota; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester; Murat R. Becer; Joao Geada (ICCAD, 2007)

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. - Rajeev R. Rao; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Transistor-Specific Delay Modeling for SSTA. - Brian Cline; Kaviraj Chopra; David T. Blaauw; Andres Torres; Savithri Sundareswaran (DATE, 2008)

A statistical approach for full-chip gate-oxide reliability analysis. - Kaviraj Chopra; Cheng Zhuo; David T. Blaauw; Dennis Sylvester (ICCAD, 2008)

Statistical Timing Analysis: From Basic Principles to State of the Art. - David T. Blaauw; Kaviraj Chopra; Ashish Srivastava; Louis Scheffer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. - Ashish Srivastava; Kaviraj Chopra; Saumil Shah; Dennis Sylvester; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Statistical Performance Analysis Optimization of Digital Circuits. - Kaviraj Chopra (2008)

Victim Alignment in Crosstalk-Aware Timing Analysis. - Ravikishore Gandikota; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques. - Vineeth Veetil; Kaviraj Chopra; David T. Blaauw; Dennis Sylvester (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis. - Cheng Zhuo; Kaviraj Chopra; Dennis Sylvester; David T. Blaauw (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)