VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. - Kavish Seth; S. Srinivasan 001 (ASP-DAC/VLSI Design, 2002)

A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. - Kavish Seth; P. Rangarajan; S. Srinivasan 001; V. Kamakoti 001; V. Bala Kuteshwar (VLSI Design, 2004)

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. - Kavish Seth; K. N. Viswajith; S. Srinivasan 001; V. Kamakoti 001 (VLSI Design, 2006)

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. - Kavish Seth; V. Kamakoti 001; S. Srinivasan 001 (IEEE Trans. Broadcast., 2010)