100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation. - Sunanda Manke; Kavita Khare; S. D. Sapre (ICON, 2008)

FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers. - Vikas Gupta; Kavita Khare; R. P. Singh (ARTCom, 2009)

Differential Delay Compensator – A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks. - Sunanda Manke; Kavita Khare; S. D. Sapre (ARTCom, 2009)

Standby leakage reduction in nanoscale CMOS VLSI circuits. - J. Deshmukh; Kavita Khare (ICWET, 2010)

VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks. - Sunanda Manke; Kavita Khare; S. D. Sapre (Eur. Trans. Telecommun., 2011)

Hardware Efficient Architecture for Generating Sine/Cosine Waves. - Supriya Aggarwal; Kavita Khare (VLSI Design, 2012)

Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm. - Supriya Aggarwal; Kavita Khare (Comput. J., 2012)

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency. - Supriya Aggarwal; Kavita Khare (Int. J. Reconfigurable Comput., 2012)

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Very Large Scale Integr. Syst., 2012)

FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems. - Sunanda Manke; Kavita Khare; S. D. Sapre (J. Signal Process. Syst., 2012)

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter. - Anita Jain; Kavita Khare (VDAT, 2013)

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline. - Supriya Aggarwal; Kavita Khare (VLSI Design, 2013)

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. - Tarun Kumar Gupta; Kavita Khare (Circuits Syst. Signal Process., 2013)

CORDIC-based window implementation to minimise area and pipeline depth. - Supriya Aggarwal; Kavita Khare (IET Signal Process., 2013)

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence. - Supriya Aggarwal; Kavita Khare (J. Signal Process. Syst., 2013)

Leakage Power Reduction Technique by using FinFET Technology. - Ajay Kumar Dadoria; Kavita Khare; R. P. Singh (ICTCS, 2016)

Low-Power High Speed 1-bit Full Adder Circuit Design. - Shailesh Dwivedi; Kavita Khare; Ajay Kumar Dadoria (ICTCS, 2016)

Concept, Design, and Implementation of Reconfigurable CORDIC. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Very Large Scale Integr. Syst., 2016)

New Leakage Reduction Techniques for FinFET Technology with Its Application. - Ajay Kumar Dadoria; Kavita Khare; Tarun Kumar Gupta; R. P. Singh (J. Circuits Syst. Comput., 2018)

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. - Ajay Kumar Dadoria; Kavita Khare (Circuits Syst. Signal Process., 2019)

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique. - Divya Gautam; Kavita Khare; Bhavana P. Shrivastava (IEEE Access, 2021)

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error. - Zainab Aizaz; Kavita Khare (Int. J. Circuit Theory Appl., 2022)

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation. - Zainab Aizaz; Kavita Khare (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. - Zainab Aizaz; Kavita Khare; Mohd Anas Khan; Mahesh Kumar Singh; Vaithiyanathan Dhandapani (APCCAS, 2023)

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. - Zainab Aizaz; Kavita Khare; Aizaz Tirmizi (FCCM, 2023)

ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs. - Zainab Aizaz; Kavita Khare (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs. - Zainab Aizaz; Kavita Khare; Aizaz Tirmizi (IEEE Embed. Syst. Lett., 2024)