Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. - Kavitha T. Madhu; Saptarsi Das; Madhava Krishna C; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. - Saptarsi Das; Kavitha T. Madhu; Madhav Krishna; Nalesh Sivanandan; Farhad Merchant; Santhi Natarajan; Ipsita Biswas; Adithya Pulli; S. K. Nandy 001; Ranjani Narayan (J. Syst. Archit., 2014)

Compiling HPC Kernels for the REDEFINE CGRA. - Kavitha T. Madhu; Saptarsi Das; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (HPCC/CSS/ICESS, 2015)

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (iNIS, 2015)

Flexible resource allocation and management for application graphs on ReNÉ MPSoC. - Kavitha T. Madhu; Anuj Rao; Saptarsi Das; Krishna C. Madhava; S. K. Nandy 001; Ranjani Narayan (PARMA-DITAM@HiPEAC, 2016)

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. - Saptarsi Das; Nalesh Sivanandan; Kavitha T. Madhu; Soumitra Kumar Nandy; Ranjani Narayan (VLSID, 2016)

REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). - Kavitha T. Madhu; Tarun Singla; S. K. Nandy 001; Ranjani Narayan; François Neumann; Philippe Baufreton (CASES, 2017)

Energy aware synthesis of application kernels through composition of data-paths on a CGRA. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (Integr., 2017)

Transport Triggered near Memory Accelerator for Deep Learning. - Kavitha T. Madhu; Saptarsi Das; Abhishek Tyagi; Ankur Deshwal; Joonho Song; Seungwon Lee (ISCAS, 2021)

Autotuning LSTM for Accelerated Execution on Edge. - Aditi Saluja; Arnab Mitra 004; Ankur Deshwal; Kavitha T. Madhu; Ujjawal Chugh; Seungwon Lee; Joonho Song (ISCAS, 2021)