Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Sylvain Clerc; Lorenzo Ciampolini; Philippe Roche (ESSCIRC, 2013)

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; Bertrand Pelloux-Prayer; Shishir Kumar; Philippe Flatresse; Christophe Lecocq; Gérard Ghibaudo (ISCAS, 2013)

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; David Turgis; Gérard Ghibaudo (ESSDERC, 2014)

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. - Fady Abouzeid; Audrey Bienfait; Kaya Can Akyel; Anis Feki; Sylvain Clerc; Lorenzo Ciampolini; Fabien Giner; Robin Wilson; Philippe Roche (IEEE J. Solid State Circuits, 2014)

DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture. - Kaya Can Akyel; Henri-Pierre Charles; Julien Mottin; Bastien Giraud; Gregory Suraci; Sébastien Thuries; Jean-Philippe Noel (ICRC, 2016)

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. - Reda Boumchedda; Jean-Philippe Noel; Bastien Giraud; Kaya Can Akyel; Melanie Brocard; David Turgis; Edith Beigné (IEEE Trans. Very Large Scale Integr. Syst., 2017)