Experience with ADAM Synthesis System. - Rajiv Jain; Kayhan Küçükçakar; Mitch J. Mlinar; Alice C. Parker (DAC, 1989)

Data Path Tradeoffs Using MABAL. - Kayhan Küçükçakar; Alice C. Parker (DAC, 1990)

CHOP: A Constraint-Driven System-Level Partitioner. - Kayhan Küçükçakar; Alice C. Parker (DAC, 1991)

A methodology and design tools to support system-level VLSI design. - Kayhan Küçükçakar; Alice C. Parker (IEEE Trans. Very Large Scale Integr. Syst., 1995)

High-level scheduling model and control synthesis for a broad range of design applications. - Chih-Tung Chen; Kayhan Küçükçakar (ICCAD, 1997)

An Architectural Power Optimization Case Study using High-level Synthesis. - Chih-Tung Chen; Kayhan Küçükçakar (ICCD, 1997)

A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis. - Chih-Tung Chen; Kayhan Küçükçakar (ISSS, 1997)

Architectural Rule Checking for High-level Synthesis. - Jie Gong; Chih-Tung Chen; Kayhan Küçükçakar (DATE, 1998)

Analysis of emerging core-based design lifecycle. - Kayhan Küçükçakar (ICCAD, 1998)

Matisse: An Architectural Design Tool for Commodity ICs. - Kayhan Küçükçakar; Chih-Tung Chen; Jie Gong; Wim Philipsen; Thomas E. Tkacik (IEEE Des. Test Comput., 1998)

An ASIP design methodology for embedded systems. - Kayhan Küçükçakar (CODES, 1999)

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. - Emre Salman; Eby G. Friedman; Ali Dasdan; Feroze Taraporevala; Kayhan Küçükçakar (ISQED, 2006)

Designing and Validating Process-Variation-Aware Cell Libraries. - Ali Dasdan; Jinfeng Liu; Sridhar Tirumala; Kayhan Küçükçakar (ISQED, 2007)

Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. - Emre Salman; Ali Dasdan; Feroze Taraporevala; Kayhan Küçükçakar; Eby G. Friedman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)