Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC. - Kazi Asifuzzaman; Milan Pavlovic; Milan Radulovic; David Zaragoza; Ohseong Kwon; Kyung-Chang Ryoo; Petar Radojkovic (MEMSYS, 2016)

Enabling a reliable STT-MRAM main memory simulation. - Kazi Asifuzzaman; Rommel Sánchez Verdejo; Petar Radojkovic (MEMSYS, 2017)

HPC Benchmarking: Scaling Right and Looking Beyond the Average. - Milan Radulovic; Kazi Asifuzzaman; Paul M. Carpenter; Petar Radojkovic; Eduard Ayguadé (Euro-Par, 2018)

Main memory latency simulation: the missing link. - Rommel Sánchez Verdejo; Kazi Asifuzzaman; Milan Radulovic; Petar Radojkovic; Eduard Ayguadé; Bruce L. Jacob (MEMSYS, 2018)

Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned. - Milan Radulovic; Kazi Asifuzzaman; Darko Zivanovic; Nikola Rajovic; Guillaume Colin de Verdière; Dirk Pleiter; Manolis Marazakis; Nikolaos D. Kallimanis; Paul M. Carpenter; Petar Radojkovic; Eduard Ayguadé (SBAC-PAD, 2018)

STT-MRAM for real-time embedded systems: performance and WCET implications. - Kazi Asifuzzaman; Mikel Fernández; Petar Radojkovic; Jaume Abella 001; Francisco J. Cazorla (MEMSYS, 2019)

Evaluation of STT-MRAM main memory for HPC and real-time systems. - Kazi Asifuzzaman (2019)

The UP2DATE Baseline Research Platforms. - Alvaro Jover-Alvarez; Alejandro J. Calderón; Iván Rodriguez; Leonidas Kosmidis; Kazi Asifuzzaman; Patrick Uven; Kim Grüttner; Tomaso Poggi; Irune Agirre (DATE, 2021)

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. - Kazi Asifuzzaman; Mohamed Abuelala; Mohamed Hassan 002; Francisco J. Cazorla (ICCAD, 2021)

Evaluating HPC Kernels for Processing in Memory. - Kazi Asifuzzaman; Mohammad Alaul Haque Monil; Frank Liu 001; Jeffrey S. Vetter (MEMSYS, 2022)

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation. - Kazi Asifuzzaman; Rommel Sánchez Verdejo; Petar Radojkovic (ACM Trans. Embed. Comput. Syst., 2022)

A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths. - Shamiul Alam; Kazi Asifuzzaman; Ahmedullah Aziz (ISQED, 2023)

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering. - Narasinga Rao Miniskar; Aaron R. Young; Kazi Asifuzzaman; Shruti R. Kulkarni; Prasanna Date; Alice Bean; Jeffrey S. Vetter (ICONS, 2024)

CMOS-Based Single-Cycle in-Memory XOR/XNOR. - Shamiul Alam; Jack Hutchins; Nikhil Shukla; Kazi Asifuzzaman; Ahmedullah Aziz (IEEE Access, 2024)

Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming. - Devin Pohl; Aaron R. Young; Kazi Asifuzzaman; Narasinga Rao Miniskar; Jeffrey S. Vetter (DATE, 2025)

ReSpike: A Co-Design Framework for Evaluating SNNs on ReRAM-Based Neuromorphic Processors. - Kazi Asifuzzaman; Aaron R. Young; Prasanna Date; Shruti R. Kulkarni; Narasinga Rao Miniskar; Matthew J. Marinella; Jeffrey S. Vetter (Euro-Par (2), 2025)

Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems. - Kazi Asifuzzaman; Narasinga Rao Miniskar; William F. Godoy; Oscar R. Hernandez; Jeffrey S. Vetter (GPGPU@PPoPP, 2025)

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM. - Shamiul Alam; Kazi Asifuzzaman; Ahmedullah Aziz (ISVLSI, 2025)

Characterizing GPU Energy Usage in Exascale-Ready Portable Science Applications. - William F. Godoy; Oscar R. Hernandez; Paul R. C. Kent; Maria Patrou; Kazi Asifuzzaman; Narasinga Rao Miniskar; Pedro Valero-Lara; Jeffrey S. Vetter; Matthew D. Sinclair; Jason Lowe-Power; Bobby R. Bruce (CoRR, 2025)