An overview of the Kyushu University reconfigurable parallel processor. - Kazuaki J. Murakami; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (SIGARCH Comput. Archit. News, 1988)

The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. - Kazuaki J. Murakami; Shin-ichiro Mori; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (ICS, 1989)

The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. - Kazuaki J. Murakami; Shin-ichiro Mori; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (IFIP Congress, 1989)

SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. - Kazuaki J. Murakami; Naohiko Irie; Morihiro Kuga; Shinji Tomita (ISCA, 1989)

Toward advanced parallel processing: exploiting parallelism at task and instruction levels. - Akira Fukuda; Kazuaki J. Murakami; Shinji Tomita (IEEE Micro, 1991)

DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. - Morihiro Kuga; Kazuaki J. Murakami; Shinji Tomita (SIGARCH Comput. Archit. News, 1991)

Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. - Tetsuo Hironaka; Takashi Hashimoto; Keizo Okazaki; Kazuaki J. Murakami; Shinji Tomita (ICS, 1992)

A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. - Takashi Hashimoto; Kazuaki J. Murakami; Tetsuo Hironaka; Hiroto Yasuura (International Conference on Supercomputing, 1993)

Optimizing the DRAM refresh count for merged DRAM/logic LSIs. - Taku Ohsawa; Koji Kai; Kazuaki J. Murakami (ISLPED, 1998)

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. - Koji Inoue; Koji Kai; Kazuaki J. Murakami (HPCA, 1999)

Way-predicting set-associative cache for high performance and low energy consumption. - Koji Inoue; Tohru Ishihara; Kazuaki J. Murakami (ISLPED, 1999)

MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation. - Koji Hashimoto; Hiroto Tomita; Koji Inoue; Katsuhiko Metsugi; Kazuaki J. Murakami; Shinjiro Inabata; So Yamada; Nobuaki Miyakawa; Hajime Takashima; Kunihiro Kitamura; Shigeru Obara; Takashi Amisaki; et al. (SC, 1999)

Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. - Koji Inoue; Koji Kai; Kazuaki J. Murakami (Intelligent Memory Systems, 2000)

Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. - Takanori Okuma; Koji Hashimoto; Kazuaki J. Murakami (ASP-DAC, 2001)

Reducing power consumption of instruction ROMs by exploiting instruction frequency. - Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (APCCAS (2), 2002)

A Low Energy Set-Associative I-Cache with Extended BTB. - Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (ICCD, 2002)

A history-based I-cache for low-energy multimedia applications. - Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (ISLPED, 2002)

Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. - Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (PACS, 2002)

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality. - Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A low-power I-cache design with tag-comparison reuse. - Koji Inoue; Hidekazu Tanaka; Vasily G. Moshnyaga; Kazuaki J. Murakami (SoC, 2004)

Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. - Makoto Sugihara; Kazuaki J. Murakami; Yusuke Matsunaga (ISVLSI, 2004)

Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (SoC, 2005)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. - Reiko Komiya; Koji Inoue; Vasily G. Moshnyaga; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Kazuaki J. Murakami; Mehdi Sedighi; Koji Inoue (Asia-Pacific Computer Systems Architecture Conference, 2006)

Circuit Area-latency Optimization Technique for High-precision Elementary Functions. - Koji Hashimoto; Vasily G. Moshnyaga; Kazuaki J. Murakami (APCCAS, 2006)

GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. - Farhad Mehdipour; Morteza Saheb Zamani; Mehdi Sedighi; Kazuaki J. Murakami; Hamid Noori (ERSA, 2006)

Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Kazuaki J. Murakami; Koji Inoue; Mehdi Sedighi (EUC, 2006)

A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. - Hamid Noori; Farhad Mehdipour; Kazuaki J. Murakami; Koji Inoue; Morteza Saheb Zamani (FPL, 2006)

Collective Communication Costs Analysis over Gigabit Ethernet and InfiniBand. - Hyacinthe Nzigou Mamadou; Takeshi Nanri; Kazuaki J. Murakami (HiPC, 2006)

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. - Farhad Mehdipour; Morteza Saheb Zamani; Hamid Reza Ahmadifar; Mehdi Sedighi; Kazuaki J. Murakami (IPDPS, 2006)

A character size optimization technique for throughput enhancement of character projection lithography. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (ISCAS, 2006)

Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications. - Hamid Noori; Kazuaki J. Murakami (SAC, 2006)

REDEFIS: a system with a redefinable instruction set processor. - Victor M. Goulart Ferreira; Lovic Gauthier; Takayuki Kando; Takuma Matsuo; Toshihiko Hashinaga; Kazuaki J. Murakami (SBCCI, 2006)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (IEICE Trans. Electron., 2006)

The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. - Hamid Noori; Maziar Goudarzi; Koji Inoue; Kazuaki J. Murakami (ESA, 2007)

Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. - Hamid Noori; Farhad Mehdipour; Kazuaki J. Murakami; Koji Inoue; Maziar Goudarzi (DATE, 2007)

Task scheduling for reliable cache architectures of multiprocessor systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (DATE, 2007)

The effect of temperature on cache size tuning for low energy embedded systems. - Hamid Noori; Maziar Goudarzi; Koji Inoue; Kazuaki J. Murakami (ACM Great Lakes Symposium on VLSI, 2007)

Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. - Hamid Noori; Farhad Mehdipour; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (ICESS, 2007)

Dynamic Optimization of Load Balance in MPI Broadcast. - Takesi Soga; Kouji Kurihara; Takeshi Nanri; Motoyoshi Kurokawa; Kazuaki J. Murakami (PVM/MPI, 2007)

Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. - Hyacinthe Nzigou Mamadou; Takeshi Nanri; Kazuaki J. Murakami; Guilherme de Melo Baptista Domingues (SBAC-PAD, 2007)

Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Inf. Syst., 2007)

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. - Mariko Sakamoto; Akira Katsuno; Go Sugizaki; Toshio Yoshida; Aiichiro Inoue; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. - Makoto Sugihara; Kenta Nakamura; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

Analyzing the impact of data prefetching on Chip MultiProcessors. - Naoto Fukumoto; Tomonobu Mihara; Koji Inoue; Kazuaki J. Murakami (ACSAC, 2008)

Design space exploration for a coarse grain accelerator. - Farhad Mehdipour; Hamid Noori; Morteza Saheb Zamani; Koji Inoue; Kazuaki J. Murakami (ASP-DAC, 2008)

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. - Hamid Noori; Farhad Mehdipour; Koji Inoue; Kazuaki J. Murakami (ISLPED, 2008)

Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. - Hamid Noori; Maziar Goudarzi; Koji Inoue; Kazuaki J. Murakami (ISVLSI, 2008)

Performance prediction of large-scale parallell system and application using macro-level simulation. - Ryutaro Susukita; Hisashige Ando; Mutsumi Aoyagi; Hiroaki Honda; Yuichi Inadomi; Koji Inoue; Shigeru Ishizuki; Yasunori Kimura; Hidemi Komatsu; Motoyoshi Kurokawa; Kazuaki J. Murakami; Hidetomo Shibamura; et al. (SC, 2008)

A gravity-directed temporal partitioning approach. - Farhad Mehdipour; Hamid Noori; Hiroaki Honda; Koji Inoue; Kazuaki J. Murakami (IEICE Electron. Express, 2008)

Performance Models for MPI Collective Communications with Network Contention. - Hyacinthe Nzigou Mamadou; Takeshi Nanri; Kazuaki J. Murakami (IEICE Trans. Commun., 2008)

Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. - Hamid Noori; Maziar Goudarzi; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Electron., 2008)

A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. - Hamid Noori; Farhad Mehdipour; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Electron., 2008)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. - Makoto Sugihara; Tohru Ishihara; Kazuaki J. Murakami (IEICE Trans. Electron., 2008)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. - Makoto Sugihara; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. - Naofumi Takagi; Kazuaki J. Murakami; Akira Fujimaki; Nobuyuki Yoshikawa; Koji Inoue; Hiroaki Honda (IEICE Trans. Electron., 2008)

An architecture framework for an adaptive extensible processor. - Hamid Noori; Farhad Mehdipour; Kazuaki J. Murakami; Koji Inoue; Morteza Saheb Zamani (J. Supercomput., 2008)

Empirical Performance Models for Java Workloads. - Pradeep Rao; Kazuaki J. Murakami (ARCS, 2009)

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. - Farhad Mehdipour; Hamid Noori; Bahman Javadi; Hiroaki Honda; Koji Inoue; Kazuaki J. Murakami (ASP-DAC, 2009)

A Dynamic Solution for Efficient MPI Collective Communications. - Hyacinthe Nzigou Mamadou; Feng Long Gu; Vivien Oddou; Takeshi Nanri; Kazuaki J. Murakami (CSO (1), 2009)

Performance balancing: software-based on-chip memory management for effective CMP executions. - Naoto Fukumoto; Kenichi Imazato; Koji Inoue; Kazuaki J. Murakami (MEDEA@PACT, 2009)

Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. - Antoine Trouvé; Lovic Gauthier; Takayuki Kando; Benoit Ryder; Sebastien Pouzols; Pradeep Rao; Norifumi Yoshimatsu; Kazuaki J. Murakami (ReConFig, 2009)

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor. - Farhad Mehdipour; Hamid Noori; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Reducing On-Chip DRAM Energy via Data Transfer Size Optimization. - Takatsugu Ono; Koji Inoue; Kazuaki J. Murakami; Kenji Yoshida (IEICE Trans. Electron., 2009)

Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode. - Pradeep Rao; Kazuaki J. Murakami (IEICE Trans. Electron., 2009)

Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. - Farhad Mehdipour; Hiroaki Honda; Hiroshi Kataoka; Koji Inoue; Irina Kataeva; Kazuaki J. Murakami; Hiroyuki Akaike; Akira Fujimaki (DATE, 2010)

Performance evaluation of 3D stacked multi-core processors with temperature consideration. - Takaaki Hanada; Hiroshi Sasaki 001; Koji Inoue; Kazuaki J. Murakami (3DIC, 2011)

A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. - Farhad Mehdipour; Krishna Chaitanya Nunna; Lovic Gauthier; Koji Inoue; Kazuaki J. Murakami (3DIC, 2011)

Routing architecture and algorithms for a superconductivity circuits-based computing hardware. - Farhad Mehdipour; Hiroaki Honda; Hiroshi Kataoka; Koji Inoue; Kazuaki J. Murakami (CCECE, 2011)

Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits. - Hadrien A. Clarke; Kazuaki J. Murakami (DSD, 2011)

Evaluation and optimization of Java object ordering schemes. - Amil A. Ilham; Kazuaki J. Murakami (ICEEI, 2011)

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers. - Hideki Miwa; Ryutaro Susukita; Hidetomo Shibamura; Tomoya Hirao; Jun Maki; Makoto Yoshida; Takayuki Kando; Yuichiro Ajima; Ikuo Miyoshi; Toshiyuki Shimizu; Yuji Oinaga; Hisashige Ando; et al. (IEICE Trans. Inf. Syst., 2011)

A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits. - Farhad Mehdipour; Hiroaki Honda; Koji Inoue; Hiroshi Kataoka; Kazuaki J. Murakami (J. Syst. Archit., 2011)

Augmenting DR-ASIP flexibility through multi-mode custom instructions. - Antoine Trouvé; Kazuaki J. Murakami (SIGARCH Comput. Archit. News, 2011)

A Three-Dimensional Integrated Accelerator. - Farhad Mehdipour; Krishna Chaitanya Nunna; Koji Inoue; Kazuaki J. Murakami (DSD, 2012)

Thermal-aware partitioning for 3D FPGAs. - Krishna Chaitanya Nunna; Farhad Mehdipour; Kazuaki J. Murakami (FPL, 2012)

A Comparison of DAG and Mesh Topologies for Coarse-Grain Reconfigurable Array. - Jonathan Antusiak; Antoine Trouvé; Kazuaki J. Murakami (IPDPS Workshops, 2012)

Power and Performance Analysis of GPU-Accelerated Systems. - Yuki Abe 001; Hiroshi Sasaki 001; Martin Peres; Koji Inoue; Kazuaki J. Murakami; Shinpei Kato (HotPower, 2012)

Methodology for early estimation of hierarchical routing resources in 3D FPGAs. - Krishna Chaitanya Nunna; Farhad Mehdipour; Masayoshi Yoshimura; Kazuaki J. Murakami (VLSI-SoC, 2012)

Optimisations Techniques for the Automatic ISA Customisation Algorithm. - Antoine Trouvé; Kazuaki J. Murakami (IEICE Trans. Inf. Syst., 2012)

PASTIS: a photonic arbitration with scalable token injection scheme. - Julien Tribino; Antoine Trouvé; Hadrien A. Clarke; Kazuaki J. Murakami (SIGARCH Comput. Archit. News, 2012)

Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization. - Hamid Noori; Farhad Mehdipour; Koji Inoue; Kazuaki J. Murakami (J. Supercomput., 2012)

Early stage power management for 3D FPGAs considering hierarchical routing resources. - Krishna Chaitanya Nunna; Farhad Mehdipour; Kazuaki J. Murakami (ACM Great Lakes Symposium on VLSI, 2013)

A Smart Cyber-physical Systems-Based Solution for Pest Control (Work in Progress). - Farhad Mehdipour; Krishna Chaitanya Nunna; Kazuaki J. Murakami (GreenCom/iThings/CPScom, 2013)

Using Machine Learning in Order to Improve Automatic SIMD Instruction Generation. - Antoine Trouvé; Arnaldo J. Cruz; Hiroki Fukuyama; Jun Maki; Hadrien A. Clarke; Kazuaki J. Murakami; Masaki Arai; Tadashi Nakahira; Eiji Yamanaka (ICCS, 2013)

MAD7: a memory architecture simulator targeted at design space exploration. - Hadrien A. Clarke; Antoine Trouvé; Kazuaki J. Murakami (ICS, 2013)

Towards Activity Recognition of Learners by Kinect. - Takuya Kamizono; Hiromichi Abe; Kensuke Baba; Shigeru Takano; Kazuaki J. Murakami (IIAI-AAI, 2014)

An Evaluation of a Complex Event Processing Engine. - Satoshi Kuboi; Kensuke Baba; Shigeru Takano; Kazuaki J. Murakami (IIAI-AAI, 2014)

A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias. - Mostafa Said; Farhad Mehdipour; Kazuaki J. Murakami; Mohamed El-Sayed 011 (MES@ISCA, 2014)

Towards activity recognition of learners by simple electroencephalographs. - Hiromichi Abe; Kensuke Baba; Shigeru Takano; Kazuaki J. Murakami (ISDOC, 2014)

Accelerated design space pruning for CMP memory architectures: work-in-progress. - Hadrien A. Clarke; Antoine Trouvé; Kazuaki J. Murakami (SpringSim (HPS), 2014)

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits. - Hiroshi Kataoka; Hiroaki Honda; Farhad Mehdipour; Nobuyuki Yoshikawa; Akira Fujimaki; Hiroyuki Akaike; Naofumi Takagi; Kazuaki J. Murakami (IEICE Trans. Electron., 2014)

Predicting Vectorization Profitability Using Binary Classification. - Antoine Trouvé; Arnaldo J. Cruz; Dhouha Ben Brahim; Hiroki Fukuyama; Kazuaki J. Murakami; Hadrien A. Clarke; Masaki Arai; Tadashi Nakahira; Eiji Yamanaka (IEICE Trans. Inf. Syst., 2014)

MAD7F: A FPGA-based CMP Memory Architecture Simulation Framework. - Hadrien A. Clarke; Kazuaki J. Murakami (CANDAR, 2015)

Analyzing Brain Waves for Activity Recognition of Learners. - Hiromichi Abe; Kazuya Kinoshita; Kensuke Baba; Shigeru Takano; Kazuaki J. Murakami (ICT-EurAsia/CONFENIS, 2015)

Interactive Visualization of Quantitative Data with G2D3. - Antoine Trouvé; Kazuaki J. Murakami (VINCI, 2015)

A survey on big data processing infrastructure: evolving role of FPGA. - Krishna Chaitanya Nunna; Farhad Mehdipour; Antoine Trouvé; Kazuaki J. Murakami (Int. J. Big Data Intell., 2015)

Towards Activity Recognition of Learners in On-line Lecture. - Hiromichi Abe; Takuya Kamizono; Kazuya Kinoshita; Kensuke Baba; Shigeru Takano; Kazuaki J. Murakami (J. Mobile Multimedia, 2015)

Guide Automatic Vectorization by means of Machine Learning: A Case Study of Tensor Contraction Kernels. - Antoine Trouvé; Arnaldo J. Cruz; Kazuaki J. Murakami; Masaki Arai; Tadashi Nakahira; Eiji Yamanaka (IEICE Trans. Inf. Syst., 2016)

An intelligent annotation-based image retrieval system based on RDF descriptions. - Hua Chen; Antoine Trouvé; Kazuaki J. Murakami; Akira Fukuda (Comput. Electr. Eng., 2017)

Exploring a Topical Representation of Documents for Recommendation Systems. - Israel Mendonça; Antoine Trouvé; Akira Fukuda; Kazuaki J. Murakami (iCAST, 2018)

Semantic image retrieval for complex queries using a knowledge parser. - Hua Chen; Antoine Trouvé; Kazuaki J. Murakami; Akira Fukuda (Multim. Tools Appl., 2018)

On Clustering Algorithms: Applications in Word-Embedding Documents. - Israel Mendonça; Antoine Trouvé; Akira Fukuda; Kazuaki J. Murakami (J. Comput., 2019)