Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. - Kazuei Hironaka; Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (FPT, 2010)

Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. - Tatsuya Yamamoto; Kazuei Hironaka; Yuki Hayakawa; Masayuki Kimura; Hideharu Amano; Kimiyoshi Usami (ARC, 2011)

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. - Kazuei Hironaka; Nobuaki Ozaki; Hideharu Amano (FPT, 2011)

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. - Masayuki Kimura; Kazuei Hironaka; Hideharu Amano (FPT, 2011)

Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. - Kazuei Hironaka; Hideharu Amano (ReConFig, 2011)

Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array. - Toru Katagiri; Kazuei Hironaka; Hideharu Amano (NBiS, 2012)

Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. - Kazuei Hironaka; Ng. Anh Vu Doan; Hideharu Amano (ARC, 2018)

Demonstration of Flow-in-Cloud: A Multi-FPGA System. - Kazuei Hironaka; Kensuke Iizuka; Akram Ben Ahmed; M. M. Imdad Ullah; Yugo Yamauchi; Yuxi Sun 001; Miho Yamakura; Aoi Hiruma; Hideharu Amano (FPL, 2019)

The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. - Miho Yamakura; Kazuei Hironaka; Keita Azegami; Kazusa Musha; Hideharu Amano (HEART, 2019)

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. - Keita Azegami; Kazusa Musha; Kazuei Hironaka; Akram Ben Ahmed; Michihiro Koibuchi; Yao Hu; Hideharu Amano (MCSoC, 2019)

Multi-FPGA Management on Flow-in-Cloud Prototype System. - Kazuei Hironaka; Akram Ben Ahmed; Hideharu Amano (SNPD, 2019)

Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. - Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Yao Hu; Michihiro Koibuchi; Hideharu Amano (CANDAR (Workshops), 2020)

Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. - Yugo Yamauchi; Akram Ben Ahmed; Kazuei Hironaka; Kensuke Iizuka; Hideharu Amano (CANDAR (Workshops), 2020)

A Method of Partitioning Convolutional Layer to Multiple FPGAs. - Kensuke Iizuka; Kohei Ito; Kazuei Hironaka; Hideharu Amano (ISOCC, 2020)

Implementing VTA, a tensor accelerator on Flow-in-Cloud. - Kazuei Hironaka; Kensuke Iizuka; Hideharu Amano (ACIT, 2021)

Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. - Tomoki Shimizu; Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Hideharu Amano (COOL CHIPS, 2021)

M-KUBOS/PYNQ Cluster for multi-access edge computing. - Takumi Inage; Kazuei Hironaka; Kensuke Iizuka; Kohei Ito; Yasuyu Fukushima; Mitaro Namiki; Hideharu Amano (CANDAR, 2021)

Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). - Kazuei Hironaka; Kensuke Iizuka; Miho Yamakura; Akram Ben Ahmed; Hideharu Amano (IEICE Trans. Inf. Syst., 2021)

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. - Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Yao Hu; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2021)

Power Analysis of Directly-connected FPGA Clusters. - Kensuke Iizuka; Haruna Takagi; Aika Kamei; Kazuei Hironaka; Hideharu Amano (COOL CHIPS, 2022)

A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. - Kazuei Hironaka; Kensuke Iizuka; Hideharu Amano (MCSoC, 2022)

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. - Tomoki Shimizu; Kohei Ito; Kensuke Iizuka; Kazuei Hironaka; Hideharu Amano (IEICE Trans. Inf. Syst., 2022)

A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. - M. M. Imdad Ullah; Akram Ben Ahmed; Kazuei Hironaka; Kensuke Iizuka; Hideharu Amano (IEICE Trans. Inf. Syst., 2023)

Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. - Kensuke Iizuka; Haruna Takagi; Aika Kamei; Kazuei Hironaka; Hideharu Amano (IEICE Trans. Inf. Syst., 2023)