Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit. - Kazuhiko Iwasaki; Noboru Yamaguchi; Yoshimune Hagiwara (Syst. Comput. Jpn., 1986)

Decoding method for shortened fire codes and its application to VLSI processor. - Kazuhiko Iwasaki; Tsuneo Funabashi; Tatsuaki Ueno (Syst. Comput. Jpn., 1987)

Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. - Tadahiko Nishimukai; Hideo Inayoshi; Kikuko Takagi; Kazuhiko Iwasaki; Ikuya Kawasaki; M. Hanawa; Takeshi Okada (ICCD, 1988)

Analysis and proposal of signature circuits for LSI testing. - Kazuhiko Iwasaki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Aliasing Probabilities and Weight Distributions of Several Codes. - Kazuhiko Iwasaki; Tadahiko Nishimukai (Syst. Comput. Jpn., 1989)

Design of signature circuits based on weight distributions of error-correcting codes. - Kazuhiko Iwasaki; Noboru Yamaguchi (ITC, 1990)

Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing. - Kazuhiko Iwasaki (Syst. Comput. Jpn., 1990)

An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel. - Kazuhiko Iwasaki; Fumio Arakawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A defect-tolerant design for mask ROMs. - Kazuhiko Iwasaki; Toru Fujiwara; Tadao Kasami (VTS, 1992)

Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers. - Marius V. A. Hâncu; Kazuhiko Iwasaki; Yuji Sato; Mamoru Sugie (Parallel Comput., 1992)

A uniform network for VLSI massively parallel computers. - Kazuhiko Iwasaki; Christian Iseli; Yuji Sato (Syst. Comput. Jpn., 1993)

A Note on Aliasing Probability for Multiple Input Signature Analyzer. - Masakatu Morii; Kazuhiko Iwasaki (IEEE Trans. Computers, 1993)

Aliasing error for a mask ROM built-in self-test. - Kazuhiko Iwasaki; Akinori Furuta; Shigeo Nakamura (VTS, 1994)

A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability. - Marius V. A. Hâncu; Kazuhiko Iwasaki; Yuji Sato; Mamoru Sugie (IEEE Trans. Parallel Distributed Syst., 1994)

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers. - Shou-ping Feng; Toru Fujiwara; Tadao Kasami; Kazuhiko Iwasaki (IEEE Trans. Computers, 1995)

Aliasing Error for a Mask ROM Built-In Self-Test. - Kazuhiko Iwasaki; Shigeo Nakamura (IEEE Trans. Computers, 1996)

Experimental fault analysis of 1 Mb SRAM chips. - Hiroyuki Goto; Shigeo Nakamura; Kazuhiko Iwasaki (VTS, 1997)

Measurement and Modeling of Burst Packet Losses in Internet End-to-End Communications. - Masayuki Arai; Atsushi Chiba; Kazuhiko Iwasaki (PRDC, 1999)

Method to Recover Internet Packet Losses Using (n, n - 1, m) Convolutional Codes. - Masayuki Arai; Anna Yamaguchi; Kazuhiko Iwasaki (DSN, 2000)

Evaluation of multicast error recovery using convolutional codes. - Anna Yamaguchi; Masayuki Arai; Kazuhiko Iwasaki (PRDC, 2000)

Hybrid BIST Using Partially Rotational Scan. - Kenichi Ichino; Takeshi Asakawa; Satoshi Fukumoto; Kazuhiko Iwasaki; Seiji Kajihara (Asian Test Symposium, 2001)

Analysis of Using Convolutional Codes to Recover Packet Losses over Burst Erasure Channels. - Masayuki Arai; Anna Yamamoto; Anna Yamaguchi; Satoshi Fukumoto; Kazuhiko Iwasaki (PRDC, 2001)

Using ATPG vectors for BIST test pattern generator. - Takeshi Asakawa; Kazuhiko Iwasaki (Syst. Comput. Jpn., 2001)

Experiment for High-Assurance Video Conference System over the Internet. - Masayuki Arai; Hitoshi Kurosu; Mamoru Ohara; Ryo Suzuki; Satoshi Fukumoto; Kazuhiko Iwasaki (HASE, 2002)

Adaptive Checkpointing for Time Warp Technique with a Limited Number of Checkpoints. - Ryo Suzuki; Satoshi Fukumoto; Kazuhiko Iwasaki (ICDCS Workshops, 2002)

Evaluation of Convolutional-Code-Based FEC under Limited Recovery Time and Its Application to Real-time Transmission. - Masayuki Arai; Hitoshi Kurosu; Satoshi Fukumoto; Kazuhiko Iwasaki (PRDC, 2002)

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. - Yuki Yamagata; Kenichi Ichino; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Masayuki Satoh; Hiroyuki Itabashi; Takashi Murai; Nobuyuki Otsuka (Asian Test Symposium, 2003)

Seed Selection Procedure for LFSR-Based Random Pattern Generators. - Kenichi Ichino; Ko-ichi Watanabe; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

BIST-oriented test pattern generator for detection of transition faults. - Takeshi Asakawa; Kazuhiko Iwasaki; Seiji Kajihara (Syst. Comput. Jpn., 2003)

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. - Masayuki Arai; Harunobu Kurokawa; Kenichi Ichino; Satoshi Fukumoto; Kazuhiko Iwasaki (Asian Test Symposium, 2004)

Finding a Recovery Line in Uncoordinated Checkpointing. - Mamoru Ohara; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (ICDCS Workshops, 2004)

Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol. - Masayuki Arai; Tabito Suzuki; Mamoru Ohara; Satoshi Fukumoto; Kazuhiko Iwasaki; Hee Yong Youn (PRDC, 2004)

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. - Kenichi Ichino; Ko-ichi Watanabe; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2004)

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. - Yasuo Sato; Iwao Yamazaki; Hiroki Yamanaka; Toshio Ikeda; Masahiro Takakura; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2004)

Analysis of error-masking and X-masking probabilities for convolutional compactors. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (ITC, 2005)

Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Expansion of Convolutional Compactors over Galois Field. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (ATS, 2006)

Test Data Compression of 100x for Scan-Based BIST. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (ITC, 2006)

Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (Comput. Math. Appl., 2006)

Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks. - Mamoru Ohara; Ryo Suzuki; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Hardware Overhead Reduction for Memory BIST. - Masayuki Arai; Kazuhiko Iwasaki; Michinobu Nakao; Iwao Suzuki (ITC, 2008)

Study on Expansion of Convolutional Compactors over Galois Field. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2008)

Study on Test Data Reduction Combining Illinois Scan and Bit Flipping. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2008)

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (IEICE Trans. Inf. Syst., 2008)

Analysis of Probabilistic Trapezoid Protocol for Data Replication. - Tabito Suzuki; Mamoru Ohara; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (J. Inf. Process., 2008)

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. - Masayuki Sato; Hiroki Wakamatsu; Masayuki Arai; Kenichi Ichino; Kazuhiko Iwasaki; Takeshi Asakawa (J. Inf. Process. Syst., 2008)

Small Delay Fault Model for Intra-Gate Resistive Open Defects. - Masayuki Arai; Akifumi Suto; Kazuhiko Iwasaki; Katsuyuki Nakano; Michihiro Shintani; Kazumi Hatayama; Takashi Aikyo (VTS, 2009)

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. - Anis Uzzaman; Brion L. Keller; Thomas J. Snethen; Kazuhiko Iwasaki; Masayuki Arai (J. Low Power Electron., 2009)

A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments. - Takahiko Ikeda; Mamoru Ohara; Satoshi Fukumoto; Masayuki Arai; Kazuhiko Iwasaki (PRDC, 2010)

Reduction of Area per Good Die for SoC Memory Built-In Self-Test. - Masayuki Arai; Tatsuro Endo; Kazuhiko Iwasaki; Michinobu Nakao; Iwao Suzuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. - Anis Uzzaman; Brion L. Keller; Brian Foutz; Sandeep Bhatia; Thomas Bartenstein; Masayuki Arai; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2010)

Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors. - Masayuki Arai; Kazuhiko Iwasaki (PRDC, 2011)

Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage. - Masayuki Arai; Yoshihiro Shimizu; Kazuhiko Iwasaki (Asian Test Symposium, 2012)

Classification of DNS Queries for Anomaly Detection. - Hongbo Shi; Kazuhiko Iwasaki (PRDC, 2013)

Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints. - Ryo Suzuki; Mamoru Ohara; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2013)

Note on Fast Bridge Fault Test Generation Based on Critical Area. - Masayuki Arai; Shingo Inuyama; Kazuhiko Iwasaki (ICA3PP (3), 2015)

Critical-Area-Aware Test Pattern Generation and Reordering. - Shingo Inuyama; Masayuki Arai; Kazuhiko Iwasaki (ATS, 2016)

Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation. - Masayuki Arai; Shingo Inuyama; Kazuhiko Iwasaki (ITC, 2017)

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage. - Masayuki Arai; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering. - Masayuki Arai; Shingo Inuyama; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)