A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Gyoo Itoh; Kazuhiko Kajigaya; Atsushi Nozoe; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

A 29-ns 64-Mb DRAM with hierarchical array architecture. - Masayuki Nakamura; Tugio Takahashi; Takesada Akiba; Goro Kitsukawa; Makoto Morino; Toshihiro Sekiguchi; Isamu Asano; Katsuo Komatsuzaki; Yoshitaka Tadaki; Songsu Cho; Kazuhiko Kajigaya; Tadashi Tachibana; et al. (IEEE J. Solid State Circuits, 1996)

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. - Hiroki Fujisawa; Takeshi Sakata; Tomonori Sekiguchi; Osamu Nagashima; Katsutaka Kimura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 1997)

A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. - Hiroki Fujisawa; Tsugio Takahashi; Masayuki Nakamura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 2001)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A low-impedance open-bitline array for multigigabit DRAM. - Tomonori Sekiguchi; Kiyoo Itoh 001; Tsugio Takahashi; Masahiro Sugaya; Hiroki Fujisawa; Masayuki Nakamura; Kazuhiko Kajigaya; Katsutaka Kimura (IEEE J. Solid State Circuits, 2002)

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Tomonori Sekiguchi; Takayuki Kawahara (ICC, 2005)

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

DRAM and eRAM. - Martin Brox; Kazuhiko Kajigaya (ISSCC, 2007)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)