Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. - Kazuhiko Terada; Masahiro Takeuchi; Kazutoshi Kobayashi; Keikichi Tamaru (ICASSP, 1998)

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. - Kazuhiko Terada; Kenji Kawai; Osamu Ishida; Keiji Kishine; Noboru Iwasaki; Haruhiko Ichino (IEICE Trans. Commun., 2005)

Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction. - Hiroyuki Uzawa; Kazuhiko Terada; Namiko Ikeda; Akihiko Miyazaki; Masami Urano; Tsugumichi Shibata (GLOBECOM, 2011)

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. - Kazuhiko Terada; Hiroyuki Uzawa; Namiko Ikeda; Satoshi Shigematsu; Nobuyuki Tanaka; Masami Urano (FPL, 2012)

High-speed sorted-table search scheme for network processing. - Hiroyuki Uzawa; Kazuhiko Terada; Namiko Ikeda; Satoshi Shigematsu (APCC, 2015)

Communication-Efficient Distributed Deep Learning with GPU-FPGA Heterogeneous Computing. - Kenji Tanaka; Yuki Arikawa; Tsuyoshi Ito; Kazutaka Morita; Naru Nemoto; Fumiaki Miura; Kazuhiko Terada; Junji Teramoto; Takeshi Sakamoto (Hot Interconnects, 2020)

A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation. - Hiroyuki Uzawa; Kazuhiko Terada; Koyo Nitta (IEICE Trans. Commun., 2021)

Distributed Deep Learning With GPU-FPGA Heterogeneous Computing. - Kenji Tanaka; Yuki Arikawa; Tsuyoshi Ito; Kazutaka Morita; Naru Nemoto; Kazuhiko Terada; Junji Teramoto; Takeshi Sakamoto (IEEE Micro, 2021)