Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. - Aika Kamei; Takuya Kojima; Hideharu Amano; Daiki Yokoyama; Hisato Miyauchi; Kimiyoshi Usami; Keizo Hiraga; Kenta Suzuki; Kazuhiro Bessho (MCSoC, 2021)

A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package. - Shota Nakabeppu; Nobuyuki Yamasaki; Kenta Suzuki; Keizo Hiraga; Kazuhiro Bessho (candar, 2023)

A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing. - Kenta Suzuki; Keizo Hiraga; Kazuhiro Bessho; Kimiyoshi Usami; Taku Umebayashi (VLSI Technology and Circuits, 2023)

A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. - Aika Kamei; Hideharu Amano; Takuya Kojima; Daiki Yokoyama; Kimiyoshi Usami; Keizo Hiraga; Kenta Suzuki; Kazuhiro Bessho (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. - Kimiyoshi Usami; Daiki Yokoyama; Aika Kamei; Hideharu Amano; Kenta Suzuki; Keizo Hiraga; Kazuhiro Bessho (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Proposal for Non-Volatilization of eFPGA Core. - Keizo Hiraga; Kenshu Seto; Kazuhiro Bessho; Masahiro Iida (COOL CHIPS, 2025)

Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP. - Keizo Hiraga; Kenshu Seto; Kazuhiro Bessho; Masahiro Iida (IPSJ Trans. Syst. LSI Des. Methodol., 2025)