A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. - Masakazu Suzuoki; Ken Kutaragi; Toshiyuki Hiroi; Hidetaka Magoshi; Shin'ichi Okamoto; Masaaki Oka; Akio Ohba; Yasuyuki Yamamoto; Makoto Furuhashi; Masayoshi Tanaka; Teiji Yutaka; Toyoshi Okada; et al. (IEEE J. Solid State Circuits, 1999)

Importance of CAD tools and methodology in high speed CPU design: invited talk. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (ASP-DAC, 2000)

CPU for PlayStation 2. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (DATE, 2001)

Towards the Profitability Trend Extraction from the Board Meeting Proceedings. - Masakazu Takahashi; Kenji Kido; Kazuhiro Hashimoto (KES, 2013)