An Instruction Decomposition Method for Reconfigurable Decoders. - Kazuhiro Yoshimura; Takashi Nakada; Yasuhiko Nakashima (IWIA, 2010)

An efficient and reliable 1.5-way processor by fusion of space and time redundancies. - Jun Yao 001; Ryoji Watanabe; Kazuhiro Yoshimura; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima (DSN Workshops, 2011)

LAPP: A Low Power Array Accelerator with Binary Compatibility. - Naveen Devisetti; Takuya Iwakami; Kazuhiro Yoshimura; Takashi Nakada; Jun Yao 001; Yasuhiko Nakashima (IPDPS Workshops, 2011)

An Instruction Mapping Scheme for FU Array Accelerator. - Kazuhiro Yoshimura; Takuya Iwakami; Takashi Nakada; Jun Yao 001; Hajime Shimada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2011)

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. - Jun Yao 001; Yasuhiko Nakashima; Naveen Devisetti; Kazuhiro Yoshimura; Takashi Nakada (IEICE Trans. Inf. Syst., 2014)

DMA-powered SDR processor exploiting DLP in LTE-Advanced. - Kazuhiro Yoshimura; Kazuo Horio; Yi Ge; Makoto Mouri; Yoshio Hirose (ICCE, 2015)

19.2 cm3 flexible fetal heart rate sensor for improved quality of pregnancy life. - Hiroyuki Sato; Kazuhiro Yoshimura; Hiroyuki Nakamoto; Daijiro Ishibashi; Yoshihiro Nakata; Yoshinori Yaginuma; Shoichi Masui (BioCAS, 2016)