An on-chip 96.5% current efficiency CMOS linear regulator. - Kazuhisa Sunaga; Tetsuo Endoh; Hiroshi Sakuraba; Fujio Masuoka (ASP-DAC, 2001)

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. - Tetsuo Endoh; Kazuhisa Sunaga; Hiroshi Sakuraba; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)

An 18Gb/s duobinary receiver with a CDR-assisted DFE. - Kazuhisa Sunaga; Hideyuki Sugita; Koichi Yamaguchi; Kazumasa Suzuki (ISSCC, 2009)

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. - Tsutomu Takeya; Kazuhisa Sunaga; Koichi Yamaguchi; Hideyuki Sugita; Yoichi Yoshida; Masayuki Mizuno; Tadahiro Kuroda (CICC, 2010)

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. - Hideyuki Sugita; Kazuhisa Sunaga; Koichi Yamaguchi; Masayuki Mizuno (ISSCC, 2010)