Module selection and data format conversion for cost-optimal DSP synthesis. - Kazuhito Ito; Lori E. Lucke; Keshab K. Parhi (ICCAD, 1994)

Automatic design for bit-serial MSPA architecture. - Hiroaki Kunieda; Yusong Liao; Dongju Li; Kazuhito Ito (ASP-DAC, 1995)

Determining the minimum iteration period of an algorithm. - Kazuhito Ito; Keshab K. Parhi (J. VLSI Signal Process., 1995)

High speed bit-serial parallel processing on array architecture. - Kazuhito Ito; Takenobu Shimizugashira; Hiroaki Kunieda (ASP-DAC, 1997)

A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. - Kazuhito Ito; Keshab K. Parhi (J. VLSI Signal Process., 1997)

ILP-based cost-optimal DSP synthesis with module selection and data format conversion. - Kazuhito Ito; Lori E. Lucke; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. - Kazuhito Ito (ASP-DAC, 2000)

H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method. - Tsuyoshi Isshiki; Chawalit Honsawek; Trio Adiono; Kazuhito Ito; Tomohiko Ohtsuka; Dongju Li; Hiroaki Kunieda (ISAS-SCI (1), 2001)

A high-level synthesis method for simultaneous placement and scheduling considering data communication delay. - Kazuhito Ito; Daisuke Suzuki (APCCAS (1), 2002)

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec. - Trio Adiono; Tsuyoshi Isshiki; Chawalit Honsawek; Kazuhito Ito; Dongju Li; Hiroaki Kunieda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Rapid and precise instruction set evaluation for application specific processor design. - Masayuki Masuda; Kazuhito Ito (ISCAS (6), 2005)

Reducing Power Dissipation of Data Communications on LSI with Scheduling Exploration. - Kazuhito Ito; Hidekazu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A Processor Accelerator for Software Decoding of BCH Codes. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI. - Hidekazu Seto; Kazuhito Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Processor Accelerator for Software Decoding of Reed-Solomon Codes. - Kazuhito Ito; Keisuke Nasu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors. - Kazuhito Ito; Takuya Numata (IEICE Trans. Electron., 2013)

Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders. - Kazuhito Ito; Ryoto Shirasaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. - Kazuhito Ito; Kazuhiko Kameda (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Development of bone-conduction mobile phones: Assessment of hearing mechanisms by measuring psychological characteristics and acoustical properties in the outer ear canal. - Seiji Nakagawa; Takuya Hotehama; Kazuhito Ito; Tomohiro Inagaki (EMBC, 2016)

Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm. - Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm. - Kazuhito Ito; Hiroki Hayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Study on interactions between voicing production and perception using auditory feedback paradigm. - Shunsuke Tamura; Miduki Mori; Kazuhito Ito; Nobuyuki Hirose; Shuji Mori (Proc. Meet. Acoust., 2017)

Mechanisms of Bone-conducted Ultrasonic Perception Assessed by Measurements of Acoustic Fields in the Outer Ear Canal and Vibrations of the Tympanic Membrane. - Seiji Nakagawa; Kazuhito Ito (EMBC, 2018)

Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution. - Kazuhito Ito; Yuto Ishihara; Shinichi Nishizawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Analog circuit design methodology utilizing a structure of thin BOX FDSOI. - Kota Chubachi; Shinichi Nishizawa; Kazuhito Ito (IEICE Electron. Express, 2019)

Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency. - Kazuhito Ito (IEICE Trans. Electron., 2020)

Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. - Yuki Imai; Shinichi Nishizawa; Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design. - Yuya Kitazawa; Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Double Modular Redundancy Design of LSI Controller for Soft Error Tolerance. - Katsutoshi Otsuka; Kazuhito Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)