Leakage power reduction for clock gating scheme on PD-SOI. - Kazuki Fukuoka; Masaaki Iijima; Kenji Hamada; Masahiro Numa; Akira Tada (ISCAS (2), 2004)

A technique for high-speed circuits on SOI using look-ahead type active body bias control. - Masaaki Iijima; Katsuya Fujita; Kazuki Fukuoka; Masahiro Numa; Keisuke Yamamoto; Kengo Takata (ISCAS (2), 2004)

A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. - Kazuki Fukuoka; Masaaki Iijima; Kenji Hamada; Masahiro Numa; Akira Tada (PATMOS, 2004)

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. - Kazuki Fukuoka; Ryo Mori; A. Kato; Motoshige Igarashi; Koji Shibutani; T. Yamaki; Shinji Tanaka; Koji Nii; Sadayuki Morita; Takao Koike; Noriaki Sakamoto (CICC, 2012)

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. - Takao Nomura; Ryo Mori; Munehiro Ito; Koji Takayanagi; Toshihiko Ochiai; Kazuki Fukuoka; Kazuo Otsuga; Koji Nii; Sadayuki Morita; Tomoaki Hashimoto; Tsuyoshi Kida; Junichi Yamada; et al. (CICC, 2013)

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. - Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; Kaname Teranishi; Kazuki Fukuoka; Noriaki Maeda; et al. (ISSCC, 2013)

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. - Kazuki Fukuoka; Noriaki Maeda; Koji Nii; Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; et al. (IEEE Micro, 2013)

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Noriaki Maeda; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; et al. (ISSCC, 2014)

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; Takeshi Kataoka; et al. (IEEE J. Solid State Circuits, 2015)

4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. - Chikafumi Takahashi; Shinichi Shibahara; Kazuki Fukuoka; Jun Matsushima; Yuko Kitaji; Yasuhisa Shimazaki; Hirotaka Hara; Takahiro Irita (ISSCC, 2016)

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. - Takao Nomura; Ryo Mori; Koji Takayanagi; Kazuki Fukuoka; Koji Nii (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. - Shinichi Shibahara; Chikafumi Takahashi; Kazuki Fukuoka; Yuko Kitaji; Takahiro Irita; Hirotaka Hara; Yasuhisa Shimazaki; Jun Matsushima (IEEE J. Solid State Circuits, 2017)

A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU. - Toshifumi Uemura; Yuko Kitaji; Kazuki Fukuoka (A-SSCC, 2019)

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. - Kenichi Shimada; Keiichiro Sano; Kazuki Fukuoka; Hiroshi Morita; Masayuki Daito; Tatsuya Kamei; Hiroyuki Hamasaki; Yasuhisa Shimazaki (ISSCC, 2023)