A Novel Local Interconnect Architecture for Variable Grain Logic Cell. - Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (ARC, 2009)

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. - Kazuki Inoue; Qian Zhao 001; Yasuhiro Okamoto; Hiroki Yosho; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (ACM Trans. Reconfigurable Technol. Syst., 2010)

An Easily Testable Routing Architecture and Efficient Test Technique. - Kazuki Inoue; Hiroki Yosho; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (FPL, 2011)

Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition. - Masahiro Toba; Yuji Hayashi; Koji Murai; Kazuki Inoue (SoSE, 2011)

An easily testable routing architecture of FPGA. - Masahiro Iida; Kazuki Inoue; Motoki Amagasaki; Toshinori Sueyoshi (VLSI-SoC, 2011)

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. - Masahiro Iida; Masahiro Koga; Kazuki Inoue; Motoki Amagasaki; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Electron., 2011)

Fault detection and avoidance of FPGA in various granularities. - Kazuki Inoue; Yuki Nishitani; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2012)

A novel physical defects recovery technique for FPGA-IP cores. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReConFig, 2012)

Evaluation of fault tolerant technique based on homogeneous FPGA architecture. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2012)

An Easily Testable Routing Architecture and Prototype Chip. - Kazuki Inoue; Masahiro Koga; Motoki Amagasaki; Masahiro Iida; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2012)

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPGA, 2013)

Defect-robust FPGA architectures for intellectual property cores in system LSI. - Motoki Amagasaki; Kazuki Inoue; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

FPGA Design Framework Combined with Commercial VLSI CAD. - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2013)

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. - Motoki Amagasaki; Yuki Nishitani; Kazuki Inoue; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2017)

Understanding Fake Faces. - Ryota Natsume; Kazuki Inoue; Yoshihiro Fukuhara; Shintaro Yamamoto; Shigeo Morishima; Hirokatsu Kataoka (ECCV Workshops (3), 2018)