A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (VLSIC, 2012)

Ring Amplifiers for Switched Capacitor Circuits. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

Parallel gain enhancement technique for switched-capacitor circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Taehwan Oh; Manideep Gande; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (CICC, 2013)

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. - Hariprasath Venkatram; Taehwan Oh; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (VLSIC, 2014)

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. - Xin Meng; Jinzhou Cao; Tao He 001; Yi Zhang 023; Gabor C. Temes; Mitsuru Aniya; Kazuki Sobue; Koichi Hamashita (ESSCIRC, 2015)

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers. - Hyuk Sun; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (A-SSCC, 2016)

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISCAS, 2016)

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (CICC, 2017)

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Kazuki Sobue; Koichi Hamashita; Gabor C. Temes (CICC, 2017)

A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. - Takato Katayama; Shiko Miyashita; Kazuki Sobue; Koichi Hamashita (VLSI Circuits, 2018)

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications. - Mahmoud Sadollahi; Koichi Hamashita; Kazuki Sobue; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Oversampling Stochastic ADC Using VCO-Based Quantizers. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier. - Ahmed ElShater; Calvin Yoji Lee; Praveen Kumar Venkatachala; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISSCC, 2019)

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier. - Ahmed ElShater; Praveen Kumar Venkatachala; Calvin Yoji Lee; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2019)

A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. - Shota Konno; Yuichi Miyahara; Kazuki Sobue; Koichi Hamashita (A-SSCC, 2020)

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (IEEE J. Solid State Circuits, 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)

A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (ISSCC, 2023)

A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Praveen Kumar Venkatachala; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (IEEE J. Solid State Circuits, 2023)