A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Yasuhiro Fujimura; Kazumasa Ando; Takeshi Kusunoki; Kunihiko Yamaguchi; Noriyuki Homma (IEEE J. Solid State Circuits, 1998)

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. - Takeshi Suzuki; Keiichi Higeta; Yasuhiro Fujimura; Kazumasa Ando; Hiroaki Nambu; Ryo Yamagata; Atsuo Hotta; Kunihiko Yamaguchi (IEEE J. Solid State Circuits, 2000)

ΔΣAD modulator for low power application. - Hajime Konagaya; HaiJun Lin; Hao San; Haruo Kobayashi 001; Kazumasa Ando; Hiroshi Yoshida; Chieto Murayama; Yukihiro Nisida (APCCAS, 2008)

Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator. - Hao San; Hajime Konagaya; Feng Xu; Atsushi Motozawa; Haruo Kobayashi 001; Kazumasa Ando; Hiroshi Yoshida; Chieto Murayama; Kanichi Miyazawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)