Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs. - Daisaburo Takashima; Shigeyoshi Watanabe; Tsuneaki Fuse; Kazumasa Sunouchi; Takahiko Hara (IEEE J. Solid State Circuits, 1993)

Memory design using a one-transistor gain cell on SOI. - Takashi Ohsawa; Katsuyuki Fujita; Tomoki Higashi; Yoshihisa Iwata; Takeshi Kajiyama; Yoshiaki Asao; Kazumasa Sunouchi (IEEE J. Solid State Circuits, 2002)

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. - Kwangmyoung Rho; Kenji Tsuchida; Dongkeun Kim; Yutaka Shirai; Jihyae Bae; Tsuneo Inaba; Hiromi Noro; Hyunin Moon; Sungwoong Chung; Kazumasa Sunouchi; Jinwon Park; Kiseon Park; et al. (ISSCC, 2017)