Enhanced Delay Test Generator for High-Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Terumine Hayashi; Masahiro Takakura; Kuniaki Kishida; Shun Ishiyama (ITC, 1989)

Sequential Test Generation Based on Real-Value Logic. - Kazumi Hatayama; Kazunori Hikone; Mitsuji Ikeda; Terumine Hayashi (ITC, 1992)

Sequential circuit test generation by real number simulation. - Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi (Syst. Comput. Jpn., 1993)

A parallel sequential test generation system DESCARTES based on real-valued logic simulation. - Hiroshi Date; Michinobu Nakao; Kazumi Hatayama (Asian Test Symposium, 1995)

Application of a Design for Delay Testability Approach to High Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Masahiro Takakura; Satoshi Uchiyama; Yoriyuki Sakamoto (Asian Test Symposium, 1997)

Accelerated Test Points Selection Method for Scan-Based BIST. - Michinobu Nakao; Kazumi Hatayama; Isao Higashi (Asian Test Symposium, 1997)

A practical approach to instruction-based test generation for functional modules of VLSI processors. - Kazumi Hatayama; Kazunori Hikone; Takeshi Miyazaki; Hiromichi Yamada (VTS, 1997)

Low overhead test point insertion for scan-based BIST. - Michinobu Nakao; Seiji Kobayashi; Kazumi Hatayama; Kazuhiko Iijima; Seiji Terada (ITC, 1999)

Test Generation for Multiple-Threshold Gate-Delay Fault Model. - Michinobu Nakao; Yoshikazu Kiyoshige; Kazumi Hatayama; Yasuo Sato; Takaharu Nagumo (Asian Test Symposium, 2001)

At-Speed Built-in Test for Logic Circuits with Multiple Clocks. - Kazumi Hatayama; Michinobu Nakao; Yasuo Sato (Asian Test Symposium, 2002)

Application of High-Quality Built-In Test to Industrial Designs. - Kazumi Hatayama; Michinobu Nakao; Yoshikazu Kiyoshige; Koichiro Natsume; Yasuo Sato; Takaharu Nagumo (ITC, 2002)

DFT timing design methodology for at-speed BIST. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Masatoshi Kawashima; Kazumi Hatayama; Kazuyuki Nomoto (ASP-DAC, 2003)

DFT Timing Design Methodology for Logic BIST. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Kazumi Hatayama; Kazuyuki Nomoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Opportunities with the open architecture test system. - Kazumi Hatayama; Rochit Rajsuman (ASP-DAC, 2004)

Session Abstract. - Kazumi Hatayama (VTS, 2006)

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. - Xiaoqing Wen; Kohei Miyase; Seiji Kajihara; Hiroshi Furukawa; Yuta Yamato; Atsushi Takashima; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Kewal K. Saluja (ETS, 2008)

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. - Kohei Miyase; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Yuta Yamato; Hiroshi Furukawa; Xiaoqing Wen; Seiji Kajihara (ICCAD, 2008)

Estimation of Delay Test Quality and Its Application to Test Generation. - Seiji Kajihara; Shohei Morishima; Masahiro Yamamoto; Xiaoqing Wen; Masayasu Fukunaga; Kazumi Hatayama; Takashi Aikyo (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato 001; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu (Asian Test Symposium, 2009)

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. - Kohei Miyase; Yuta Yamato; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Xiaoqing Wen; Seiji Kajihara (ICCAD, 2009)

Small Delay Fault Model for Intra-Gate Resistive Open Defects. - Masayuki Arai; Akifumi Suto; Kazuhiko Iwasaki; Katsuyuki Nakano; Michihiro Shintani; Kazumi Hatayama; Takashi Aikyo (VTS, 2009)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

Foreword. - Kazumi Hatayama; Tsuyoshi Shinogi (IEICE Trans. Inf. Syst., 2010)

A Study of Capture-Safe Test Generation Flow for At-Speed Testing. - Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Atsushi Takashima; Hiroshi Furukawa; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Kewal K. Saluja (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. - Kohei Miyase; Kenji Noda; Hideaki Ito; Kazumi Hatayama; Takashi Aikyo; Yuta Yamato; Hiroshi Furukawa; Xiaoqing Wen; Seiji Kajihara (IEICE Trans. Inf. Syst., 2011)

DART: Dependable VLSI test architecture and its implementation. - Yasuo Sato; Seiji Kajihara; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue; Yukiya Miura; Satosni Untake; Takumi Hasegawa; Motoyuki Sato; Kotaro Shimamura (ITC, 2012)

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. - Yuta Yamato; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue (ITC, 2012)

Special session 4B: Elevator talks. - Jennifer Dworak; Ronald Shawn Blanton; Masahiro Fujita; Kazumi Hatayama; Naghmeh Karimi; Michail Maniatakos; Antonis M. Paschalis; Adit D. Singh; Tian Xia (VTS, 2013)

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. - Yussuf Ali; Yuta Yamato; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue (ATS, 2014)

Memory block based scan-BIST architecture for application-dependent FPGA testing. - Keita Ito; Tomokazu Yoneda; Yuta Yamato; Kazumi Hatayama; Michiko Inoue (FPGA, 2014)

A Variability-Aware Adaptive Test Flow for Test Quality Improvement. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. - Michihiro Shintani; Takumi Uezono; Kazumi Hatayama; Kazuya Masu; Takashi Sato 001 (J. Electron. Test., 2016)

Innovative practices session 9B innovative practices in Asia-1: From quality perspective. - Kazumi Hatayama; Masahiro Ishida (VTS, 2017)

Innovative practices session 10B innovative practices in Asia-2: From cost perspective. - Kazumi Hatayama; Masahiro Ishida (VTS, 2017)

Innovative practices on test in Japan. - Koji Asami; Yoshiro Tamura; Haruo Kobayashi 001; Jun Matsushima; Yoichi Maeda; Kazumi Hatayama (VTS, 2018)

Evaluation of Null Method for Operational Amplifier Short-Time Testing. - Riho Aoki; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Yuto Sasaki; Kosuke Machida; Takayuki Nakatani; Jianlong Wang; Anna Kuwana; Kazumi Hatayama; et al. (ASICON, 2019)

High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. - Jiang-Lin Wei; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Nene Kushita; Takahiro Arai; Lei Sha; Anna Kuwana; Haruo Kobayashi 001; Takayuki Nakatani; Kazumi Hatayama; Keno Sato (ASICON, 2019)

Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. - Yuto Sasaki; Kosuke Machida; Riho Aoki; Shogo Katayama; Takayuki Nakatani; Jianlong Wang; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Anna Kuwana; Kazumi Hatayama; et al. (ITC-Asia, 2019)

Innovative Test Practices in Japan. - Yusuke Asada; Takahiko Shimizu; Yuji Gendai; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Jiang-Lin Wei; Nene Kushita; Hirotaka Arai; Anna Kuwana; Takayuki Nakatani; et al. (VTS, 2019)

Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. - Gaku Ogihara; Takayuki Nakatani; Akemi Hatta; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Anna Kuwana; Riho Aoki; Shogo Katayama; Jianglin Wei; Yujie Zhao; et al. (ATS, 2020)

Accurate Testing of Precision Voltage Reference by DC-AC Conversion. - Keno Sato; Takayuki Nakatani; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Anna Kuwana; Kazumi Hatayama; Haruo Kobayashi 001 (ATS, 2020)

Innovative Test Practices in Asia. - Takeshi Iwasaki; Masao Aso; Haruji Futami; Satoshi Matsunaga; Yousuke Miyake; Takaaki Kato; Seiji Kajihara; Yukiya Miura; Smith Lai; Gavin Hung; Harry H. Chen; Haruo Kobayashi 001; et al. (VTS, 2020)

High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. - Keno Sato; Takayuki Nakatani; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Gaku Ogihara; Daisuke Iimori; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kazumi Hatayama; et al. (ATS, 2021)

Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production. - Gaku Ogihara; Takayuki Nakatani; Daisuke Iimori; Shogo Katayama; Anna Kuwana; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Yujie Zhao; Jianglin Wei; Kazumi Hatayama; et al. (ICECS, 2021)

Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. - Shuhei Yamamoto; Yuto Sasaki; Yujie Zhao; Jianglin Wei; Anna Kuwana; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Takayuki Nakatani; Minh Tri Tran 001; Shogo Katayama; et al. (IOLTS, 2021)

Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. - Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Akemi Hatta; Anna Kuwana; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Jianglin Wei; Yujie Zhao; et al. (ITC, 2021)

Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. - Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Jianglin Wei; Takayuki Nakatani; Yujie Zhao; Shogo Katayama; Shuhei Yamamoto; Anna Kuwana; Kazumi Hatayama; Haruo Kobayashi 001 (ITC, 2021)

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. - Keno Sato; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Kazumi Hatayama; et al. (ATS, 2022)

Innovative Practices Track: Innovative Analog Circuit Testing Technologies. - Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; et al. (VTS, 2022)

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. - Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Jianglin Wei; Haruo Kobayashi 001; Takayuki Nakatani; Kazumi Hatayama; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa (J. Electron. Test., 2022)

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. - Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi 001; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; et al. (ITC-Asia, 2023)

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. - Keno Sato; Takayuki Nakatani; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Shuhei Yamamoto; Anna Kuwana; Kentaroh Katoh; et al. (ITC, 2023)

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. - Shogo Katayama; Takayuki Nakatani; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; et al. (IEICE Electron. Express, 2023)