Towards Reconfigurable Cache Memory for a Multithreaded Processor. - Yoshiyasu Ogasawara; Ippei Tate; Satoshi Watanabe; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

A Model of Implementable SMT Processor on FPGA. - Ippei Tate; Yoshiyasu Ogasawara; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Satoshi Watanabe; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)